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1. 发明授权

US4163280A Address management system 失效
标题翻译：地址管理系统
公开(公告)号：US4163280A
公开(公告)日：1979-07-31
申请号：US807500
申请日：1977-06-17
申请人： Ryuichi Mori , Tadao Ichikawa , Yukio Shiraogawa
发明人： Ryuichi Mori , Tadao Ichikawa , Yukio Shiraogawa
IPC分类号： G06F12/02 , G06F12/06 , G06F12/10 , G11C29/00 , G06F3/00 , G06F5/00 , G06F9/20 , G06F13/00
CPC分类号： G11C29/76 , G06F12/0292 , G06F12/0638 , G06F12/1081
摘要： An address management system includes a central processing unit (CPU) and an address management unit arranged between a direct memory device (DMA) and a main memory unit to control memory access from the CPU and DMA. Segment registers for address expansion are provided in the CPU and DMA, respectively. The address management unit includes a conversion table for converting logical address data and segment data and segment data from the CPU and DMA into a corresponding physical address data, and the conversion table includes a bit position for detecting an address error and a control bit for selecting a memory access to a local memory or a shared memory.
摘要翻译：地址管理系统包括中央处理单元（CPU）和布置在直接存储器件（DMA）和主存储器单元之间的地址管理单元，用于控制来自CPU和DMA的存储器访问。 CPU和DMA分别提供用于地址扩展的段寄存器。地址管理单元包括用于将来自CPU和DMA的逻辑地址数据和段数据以及段数据转换成相应的物理地址数据的转换表，并且转换表包括用于检测地址错误的位位置和用于选择的控制位对本地存储器或共享存储器的存储器访问。

2. 发明授权

US4653110A Image processor system 失效
标题翻译：图像处理器系统
公开(公告)号：US4653110A
公开(公告)日：1987-03-24
申请号：US792848
申请日：1985-10-30
申请人： Yukio Urushibata , Yukio Shiraogawa
发明人： Yukio Urushibata , Yukio Shiraogawa
IPC分类号： G06T3/00 , G06F15/17 , G06T1/20 , G06K9/00
CPC分类号： G06F15/17 , G06T1/20
摘要： In the image processor system of the invention, an image processor and a plurality of image memories are connected through a plurality of image buses. The image processor and image memories are also connected through a control bus, as is a CPU. The image processor has a start signal output gate circuit. When the gate circuit is initiated by the CPU, it simultaneously outputs start signals designating image data output to the image buses designated by the CPU. Each image memory has a start signal input gate circuit and an output gate circuit. The start input gate circuit receives the start signal from the image bus designated by the CPU through the control bus. The output gate circuit starts image data output to the designated image bus in response to the start signal received at the start signal input gate circuit and in synchronism with the bus cycle of the image bus.
摘要翻译：在本发明的图像处理器系统中，通过多个图像总线连接图像处理器和多个图像存储器。图像处理器和图像存储器也通过控制总线连接，CPU也是如此。图像处理器具有启动信号输出门电路。当门电路由CPU启动时，它同时输出指定图像数据输出到由CPU指定的图像总线的起始信号。每个图像存储器具有启动信号输入门电路和输出门电路。启动输入门电路通过控制总线从CPU指定的图像总线接收启动信号。输出门电路响应于在起始信号输入门电路处接收到的起始信号并与图像总线的总线周期同步地开始输出到指定图像总线的图像数据。

3. 发明授权

US4314332A Memory control system 失效
标题翻译：内存控制系统
公开(公告)号：US4314332A
公开(公告)日：1982-02-02
申请号：US20021
申请日：1979-03-13
申请人： Yukio Shiraogawa , Keizo Aoyagi
发明人： Yukio Shiraogawa , Keizo Aoyagi
IPC分类号： G06F9/34 , G06F12/04 , G06F9/06
CPC分类号： G06F9/34
摘要： Disclosed is a memory control system for a data processing system in which the length of an access unit to a memory can be different from the lengths of information words which can be processed and which can include data, addresses, and instructions and operands processed in an arithmetic control apparatus, and combinations thereof. The disclosed memory control system provides an address boundary for effecting a read/write operation with respect to the memory of information words having a half-word length and a full-word length. The half-word length information words can correspond to 2n times a minimum word length, n being a positive integer, and the access unit length can be equal to the minimum unit word length. In a disclosed embodiment, the minimum unit word length and the access unit length can be an 8 bit byte. Thus, a half-word length can be 16 bits and a full-word length can be 32 bits.
摘要翻译：公开了一种用于数据处理系统的存储器控制系统，其中存储器的访问单元的长度可以与可以处理的信息字的长度不同，并且可以包括数据，地址以及在算术控制装置及其组合。所公开的存储器控制系统提供用于对具有半字长度和全字长度的信息字的存储器进行读/写操作的地址边界。半字长度信息字可以对应于最小字长的2n倍，n是正整数，并且存取单元长度可以等于最小单位字长。在公开的实施例中，最小单位字长度和存取单元长度可以是8位字节。因此，半字长可以是16位，全字长度可以是32位。

4. 发明授权

US4414626A Input/output control system and methods 失效
标题翻译：输入/输出控制系统和方法
公开(公告)号：US4414626A
公开(公告)日：1983-11-08
申请号：US213579
申请日：1980-12-05
申请人： Michio Arai , Yukio Shiraogawa , Tsutomu Sakamoto , Keizo Aoyagi
发明人： Michio Arai , Yukio Shiraogawa , Tsutomu Sakamoto , Keizo Aoyagi
IPC分类号： G06F13/12 , G06F1/00
CPC分类号： G06F13/122
摘要： An input/output start instruction includes, as parameters, a channel number, an input/output device number, a channel control block address and a termination que number. A channel receives the channel control block address and reads out the contents of the channel control block from a main memory and sets it in a service table in the channel whereby an input/output processing is executed.
摘要翻译：作为参数，输入/输出开始指令包括通道号，输入/输出设备号，通道控制块地址和终止号码。信道接收信道控制块地址并从主存储器读出信道控制块的内容，并将其设置在通道中的服务表中，从而执行输入/输出处理。

5. 发明授权

US4245301A Information processing system 失效
标题翻译：信息处理系统
公开(公告)号：US4245301A
公开(公告)日：1981-01-13
申请号：US930406
申请日：1978-08-02
申请人： Takashi Rokutanda , Yukio Shiraogawa , Yutaka Nakajima , Keizo Aoyagi , Takashi Hiraoka
发明人： Takashi Rokutanda , Yukio Shiraogawa , Yutaka Nakajima , Keizo Aoyagi , Takashi Hiraoka
IPC分类号： G06F13/36 , G06F13/362 , G06F13/40 , G06F15/16 , G06F9/46
CPC分类号： G06F13/362 , G06F13/4027 , G06F13/4031 , G06F15/161
摘要： An information processing system having a main memory unit, an arithmetic control unit, and a plurality of input/output units, is comprised of a first bus, which is bidirectional, commonly connecting the main memory unit, the arithmetic control unit, and at least one input/output unit, a bus controller for controlling data transfer between two units connecting to the first bus, a second bus, which is also bidirectional, commonly connecting to the arithmetic control unit with at least another input/output unit, and a bus control means which is provided in the arithmetic control unit and controls data transfer between two units connecting to the second bus. The information processing system uses various units connecting to the first and second buses in time sharing and multiplexing mode.
摘要翻译：具有主存储单元，运算控制单元和多个输入/输出单元的信息处理系统由第一总线构成，第一总线是双向的，通常连接主存储单元，算术控制单元，并且至少一个输入/输出单元，用于控制连接到第一总线的两个单元之间的数据传输的总线控制器，也是双向的第二总线，通常使用至少另一个输入/输出单元连接到算术控制单元控制装置，设置在算术控制单元中，并控制连接到第二总线的两个单元之间的数据传送。信息处理系统使用在时分和复用模式下连接到第一和第二总线的各种单元。

6. 发明授权

US4131943A Microprogrammed computer employing a decode read only memory (DROM) and a microinstruction read only memory (ROM) 失效
标题翻译：采用解码只读存储器（DROM）和微指令只读存储器（ROM）的微编程计算机
公开(公告)号：US4131943A
公开(公告)日：1978-12-26
申请号：US807499
申请日：1977-06-17
申请人： Yukio Shiraogawa
发明人： Yukio Shiraogawa
IPC分类号： G06F9/22 , G06F9/26 , G06F9/16 , G06F13/00
CPC分类号： G06F9/261
摘要： A microprogrammed computer comprises an instruction register for registering a machine instruction word; a decode read only memory (DROM) for storing the start address data of microprogram routines which correspond to machine instruction words, respectively, and the control bit data which correspond to the machine instruction words, respectively; and a read only memory (ROM) for storing a plurality of microprograms each consisting of microinstructions. The microprogrammed computer has such a hardware structure that each control bit datum in the DROM may serve to change the function of a microinstruction and the execution sequence of the microprograms in the ROM.
摘要翻译：微程序计算机包括用于登记机器指令字的指令寄存器; 解码只读存储器（DROM），用于分别存储对应于机器指令字的微程序例程的起始地址数据和对应于机器指令字的控制位数据; 以及用于存储由微指令组成的多个微程序的只读存储器（ROM）。微程序计算机具有这样的硬件结构，即DROM中的每个控制位数据可以用于改变微指令的功能和ROM中微程序的执行顺序。

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