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1. 发明授权

US5708399A Modulator and frequency multiplier for use therein 失效
标题翻译：用于其中的调制器和倍频器
公开(公告)号：US5708399A
公开(公告)日：1998-01-13
申请号：US674506
申请日：1996-07-02
申请人： Ryota Fujii , Masahiro Tsukahara , Moriaki Mizuno , Minoru Takagi
发明人： Ryota Fujii , Masahiro Tsukahara , Moriaki Mizuno , Minoru Takagi
IPC分类号： H03D7/14 , H03B19/14 , H03C3/14 , H03D7/16 , H03B19/10 , H03C3/00
CPC分类号： H03D7/16
摘要： A modulator that effectively suppresses carrier leakage is disclosed. The modulator includes a frequency multiplier, a phase shifter and an orthogonal modulator. The frequency multiplier outputs complementary signals whose frequencies are twice the frequency of a first carrier signal. The phase shifter divides the frequencies of the output signals of the frequency multiplier to produce a plurality of second carrier signals whose phases are shifted by 90 degrees from one another. The orthogonal modulator receives an input signal and the second carrier signals from the phase shifter and outputs signals obtained by combining the input signal with the second carrier signals. The frequency multiplier has an input circuit section including a differential circuit. The differential input section receives complementary signals as the first carrier signal. The orthogonal modulator has an output circuit section including a differential circuit.
摘要翻译：公开了一种有效抑制载流子泄漏的调制器。调制器包括倍频器，移相器和正交调制器。倍频器输出其频率是第一载波信号频率的两倍的互补信号。移相器分频倍频器的输出信号的频率，产生相位彼此相差90度的多个第二载波信号。正交调制器从移相器接收输入信号和第二载波信号，并输出通过将输入信号与第二载波信号组合而获得的信号。倍频器具有包括差动电路的输入电路部分。差分输入部分接收互补信号作为第一载波信号。正交调制器具有包括差分电路的输出电路部分。

2. 发明授权

US5162676A Circuit having level converting circuit for converting logic level 失效
标题翻译：具有转换逻辑电平的电平转换电路的电路
公开(公告)号：US5162676A
公开(公告)日：1992-11-10
申请号：US669987
申请日：1991-03-15
申请人： Kouju Aoki , Hideji Sumi , Moriaki Mizuno , Tetsuya Aisaka
发明人： Kouju Aoki , Hideji Sumi , Moriaki Mizuno , Tetsuya Aisaka
IPC分类号： H03K19/018 , H03K19/086
CPC分类号： H03K19/01812 , H03K19/086
摘要： A circuit has a level converting circuit for converting a signal having level in conformance with a first logic system into a signal having a level in conformance with a second logic system. The circuit includes first, second and third voltage lines for respectively supplying first, second and third power source voltages, a level converting circuit coupled to the first and third voltage lines for converting a first signal having a level in conformance with the first logic system into a second signal having a level in conformance with the second logic system, a reference voltage generating part coupled to the first and third voltage lines for generating a reference voltage based on at least the first power source voltage, so that the reference voltage undergoes a corresponding level deviation with respect to a level deviation of the second signal caused by a level deviation in the first signal which occurs due to a level deviation in the first power source voltage, and a logic circuit which employs the second logic system and is coupled to the second and third voltage lines for receiving the second signal from the level converting circuit and for outputting an output signal using the reference voltage from the reference voltage generating part as a bias signal. The first power source voltage is a positive voltage relative to the second power source voltage and the third power source voltage is a negative voltage relative to the second power source voltage.

3. 发明授权

US5248909A ECL-to-GaAs level converting circuit 失效
标题翻译： ECL-TO-GaAs电平转换电路
公开(公告)号：US5248909A
公开(公告)日：1993-09-28
申请号：US919371
申请日：1992-07-29
申请人： Kouju Aoki , Hideji Sumi , Moriaki Mizuno , Tetsuya Aisaka
发明人： Kouju Aoki , Hideji Sumi , Moriaki Mizuno , Tetsuya Aisaka
IPC分类号： H03K19/003 , H03K19/018
CPC分类号： H03K19/01812 , H03K19/00376
摘要： A level converting circuit converts a first signal which has an ECL level which is used in an ECL device into a second signal which has a GaAs logic level which is used in a GaAs device which is based on a GaAs substrate.
摘要翻译：电平转换电路将具有ECL装置中使用的ECL电平的第一信号转换为具有基于GaAs衬底的GaAs器件中使用的GaAs逻辑电平的第二信号。

4. 发明授权

US5594382A Constant voltage circuit 失效
标题翻译：恒压电路
公开(公告)号：US5594382A
公开(公告)日：1997-01-14
申请号：US407248
申请日：1995-03-20
申请人： Susumu Kato , Moriaki Mizuno , Kazumi Ogawa , Kazuyuki Nonaka
发明人： Susumu Kato , Moriaki Mizuno , Kazumi Ogawa , Kazuyuki Nonaka
IPC分类号： G05F3/30 , G05F3/26 , G05F1/10 , G05F3/02
CPC分类号： G05F3/267
摘要： A constant voltage circuit adapted for connection between high voltage power source and low voltage power source terminals respectively to output a constant voltage signal from an output terminal in response to a control signal inputted to an input terminal. The circuit has a resistor circuit including a MOS transistor for connection to the high voltage power source and activated in response to the control signal. A current mirror section is connected between the resistor circuit and the low voltage power source terminal to generate an output voltage to be outputted from the output terminal. A feedback section is connected between the resistor circuit and the low voltage power source terminal to control the current mirror section to keep the output voltage constant by detecting deviation of the output voltage.
摘要翻译：一种恒压电路，分别适于连接高电压电源和低电压电源端子，以响应输入到输入端子的控制信号从输出端输出恒定电压信号。电路具有包括用于连接到高电压电源并且响应于控制信号激活的MOS晶体管的电阻器电路。电流镜部分连接在电阻器电路和低压电源端子之间，以产生从输出端子输出的输出电压。反馈部分连接在电阻电路和低压电源端子之间，以通过检测输出电压的偏差来控制电流镜部分以保持输出电压恒定。

5. 发明授权

US5424590A Delay time control circuit 失效
标题翻译：延时控制电路
公开(公告)号：US5424590A
公开(公告)日：1995-06-13
申请号：US79799
申请日：1993-06-23
申请人： Kenichi Sato , Moriaki Mizuno , Kouju Aoki
发明人： Kenichi Sato , Moriaki Mizuno , Kouju Aoki
IPC分类号： H03K5/13 , H03K3/26 , H03K5/159
CPC分类号： H03K5/131
摘要： An input signal is provided at first input terminals of a plurality of parallel AND gates in a delay time control circuit. A digital signal from a decoder having a plurality of bits is coupled to second input terminals of the AND gates with one bit coupled per AND gate. The decoder outputs a signal having an a high level in response to an external input control signal. Output signals from the AND gates are coupled to inputs of a plurality of serially connected OR gates.
摘要翻译：输入信号设置在延迟时间控制电路中的多个并行与门的第一输入端。来自具有多个位的解码器的数字信号被耦合到与门的第二输入端，每个与门耦合一位。解码器响应于外部输入控制信号输出具有高电平的信号。与门的输出信号耦合到多个串联OR门的输入端。

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