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    • 1. 发明授权
    • Network apparatus that determines whether data is written into buffer based on detection of a memory error
    • 基于检测到存储器错误确定数据是否被写入缓冲器的网络设备
    • US08295161B2
    • 2012-10-23
    • US12639086
    • 2009-12-16
    • Ryoji AzumiTakashi UmegakiShigeo TaniShosaku Yamasaki
    • Ryoji AzumiTakashi UmegakiShigeo TaniShosaku Yamasaki
    • H04L1/22
    • H04J3/14H04J2203/006
    • A network apparatus includes: an input interface unit; a first and second line switching units cross-connecting output signals from the input interface unit; an output interface unit including a selection unit selecting outputs from the first or second line switching units; and a CPU. The line switching units each include: a control signal generation unit storing setting data in a memory and generating a line switching control signal based on the setting data; a memory error detection processing unit detecting a memory error and outputting error information; and a main signal processing unit writing setting data into a buffer when an error is not detected, and holding setting data stored in the buffer when the error is detected, and which performs cross-connection processing according to the setting data stored in the buffer. The CPU controls the selection unit according to the error information.
    • 网络装置包括:输入接口单元; 第一和第二线路交换单元将来自输入接口单元的输出信号交叉连接; 输出接口单元,包括:选择单元,用于选择来自第一或第二行切换单元的输出; 和一个CPU。 线路切换单元各自包括:控制信号生成单元,其将设置数据存储在存储器中,并且基于设置数据生成线路切换控制信号; 存储器错误检测处理单元,检测存储器错误并输出错误信息; 以及主信号处理单元,当未检测到错误时将设置数据写入缓冲器,并且当检测到错误时保持存储在缓冲器中的设置数据,并且根据存储在缓冲器中的设置数据执行交叉连接处理。 CPU根据错误信息控制选择单元。
    • 2. 发明申请
    • NETWORK APPARATUS
    • 网络设备
    • US20100158514A1
    • 2010-06-24
    • US12639086
    • 2009-12-16
    • Ryoji AZUMITakashi UmegakiShigeo TaniShosaku Yamasaki
    • Ryoji AZUMITakashi UmegakiShigeo TaniShosaku Yamasaki
    • H04B10/08H04B10/02
    • H04J3/14H04J2203/006
    • A network apparatus includes: an input interface unit; a first and second line switching units cross-connecting output signals from the input interface unit; an output interface unit including a selection unit selecting outputs from the first or second line switching units; and a CPU. The line switching units each include: a control signal generation unit storing setting data in a memory and generating a line switching control signal based on the setting data; a memory error detection processing unit detecting a memory error and outputting error information; and a main signal processing unit writing setting data into a buffer when an error is not detected, and holding setting data stored in the buffer when the error is detected, and which performs cross-connection processing according to the setting data stored in the buffer. The CPU controls the selection unit according to the error information.
    • 网络装置包括:输入接口单元; 第一和第二线路交换单元将来自输入接口单元的输出信号交叉连接; 输出接口单元,包括:选择单元,用于选择来自第一或第二行切换单元的输出; 和一个CPU。 线路切换单元各自包括:控制信号生成单元,其将设置数据存储在存储器中,并且基于设置数据生成线路切换控制信号; 存储器错误检测处理单元,检测存储器错误并输出错误信息; 以及主信号处理单元,当未检测到错误时将设置数据写入缓冲器,并且当检测到错误时保持存储在缓冲器中的设置数据,并且根据存储在缓冲器中的设置数据执行交叉连接处理。 CPU根据错误信息控制选择单元。
    • 9. 发明授权
    • Clock device
    • 时钟设备
    • US08564355B2
    • 2013-10-22
    • US13004438
    • 2011-01-11
    • Shigeo TaniTakashi Umegaki
    • Shigeo TaniTakashi Umegaki
    • H03K3/00
    • G06F1/06G06F11/0754H03L7/095H03L7/22
    • There is provided a clock device including: a clock circuit to generate a plurality of clock signals, the clock circuit including a reset part for resetting generation of the clock signals; and a peripheral circuit operating based on the clock signals generated from the clock circuit, the peripheral circuit including: an error detection part for detecting an error in a process performed in the peripheral circuit by using the clock signals, and a determination part for determining whether to reset the clock circuit, based on information of the error detected by the error detection part.
    • 提供了一种时钟装置,包括:产生多个时钟信号的时钟电路,所述时钟电路包括用于复位时钟信号的产生的复位部分; 以及基于从时钟电路产生的时钟信号而工作的外围电路,所述外围电路包括:误差检测部,其通过使用所述时钟信号来检测在所述外围电路中执行的处理中的错误;判定部, 基于由错误检测部检测到的错误的信息来复位时钟电路。