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1. 发明授权

US07720897B2 Optimized discrete fourier transform method and apparatus using prime factor algorithm 有权
标题翻译：优化离散傅里叶变换方法和设备使用素因子算法
公开(公告)号：US07720897B2
公开(公告)日：2010-05-18
申请号：US11400566
申请日：2006-04-07
申请人： Ryan Samuel Buchert , Sharif M. Shahrier , Peter Edward Becker
发明人： Ryan Samuel Buchert , Sharif M. Shahrier , Peter Edward Becker
IPC分类号： G06F17/14
CPC分类号： G06F17/144
摘要： An apparatus and method for DFT processing using prime factor algorithm (PFA) on a selected number P of midamble chip values received by a CDMA receiver, where P has a plurality M of relatively prime factors F, and the DFT process is divided into M successive F-point DFT processes. The P data values are retrieved from a single input port memory and selectively permuted by a controller into parallel caches to optimize factoring with associated twiddle factors stored in parallel registers. The permuted inputs are factored in two or more parallel PFA circuits that comprise adders and multipliers arranged to accommodate any size F-point DFT. The outputs of the PFA circuits are processed by consolidation circuitry in preparation for output permutation of the values which are sent to memory for subsequent DFT cycles.
摘要翻译：一种用于使用素数因子算法（PFA）对由CDMA接收机接收的中间码片值的选定数目P进行DFT处理的装置和方法，其中P具有多个相对素数因子F，并且DFT处理被分成M个连续 F点DFT处理。从单个输入端口存储器检索P数据值，并由控制器选择性地置换为并行高速缓存，以使存储在并行寄存器中的相关旋转因子优化因子分解。经置换的输入在两个或多个并行PFA电路中被考虑，其中包括加法器和乘法器，其被布置成适应任何尺寸的F点DFT。 PFA电路的输出由合并电路处理，准备输出置换到发送到存储器以用于随后的DFT周期的值。

2. 发明授权

US07031284B2 Wireless communication method and apparatus for optimizing multi-user detection 失效
标题翻译：用于优化多用户检测的无线通信方法和装置
公开(公告)号：US07031284B2
公开(公告)日：2006-04-18
申请号：US10725808
申请日：2003-12-02
申请人： Stephan Shane Supplee , Chayil S. Timmerman , Ryan Samuel Buchert , Peter Edward Becker , Tonino Nasuti , Robert A. DiFazio , John W. Haim
发明人： Stephan Shane Supplee , Chayil S. Timmerman , Ryan Samuel Buchert , Peter Edward Becker , Tonino Nasuti , Robert A. DiFazio , John W. Haim
IPC分类号： H04B7/216
CPC分类号： H04B1/71052 , H04B2201/70707
摘要： Multi-user detection (MUD) performance is optimized to eliminate redundant use of power during processing. An overbuilt A-matrix, i.e., a system response matrix, is provided. The overbuilt A-matrix uses all possible codes, e.g., all codes identified in a candidate code list (CCL) provided by blind code detection (BCD). The overbuilt A-matrix is passed to the MUD which extracts only those rows or columns required for codes that have actually been received, thus eliminating the need to recompute whitening matched filter (WMF) outputs that do not correspond to the actually received code.
摘要翻译：优化多用户检测（MUD）性能，以消除处理过程中冗余电源的使用。提供了一种过度建立的A矩阵，即系统响应矩阵。过量的A矩阵使用所有可能的代码，例如由盲代码检测（BCD）提供的候选代码表（CCL）中标识的所有代码。过量的A矩阵被传递给仅提取实际已经接收的代码所需的行或列的MUD，从而不需要重新计算与实际接收的代码不对应的白化匹配滤波器（WMF）输出。

3. 发明授权

US06959034B2 CDMA system transmission matrix coefficient calculation 失效
标题翻译： CDMA系统传输矩阵系数计算
公开(公告)号：US06959034B2
公开(公告)日：2005-10-25
申请号：US10920137
申请日：2004-08-17
申请人： Ryan Samuel Buchert , Chayil S. Timmerman , Peter Edward Becker , Muhammad Usman Fazili
发明人： Ryan Samuel Buchert , Chayil S. Timmerman , Peter Edward Becker , Muhammad Usman Fazili
IPC分类号： H04B1/707 , H03M13/23 , H04B1/7093 , H04B7/155 , H04B7/216 , H04K1/00
CPC分类号： H04B1/7093 , H04B2201/70707
摘要： An apparatus and method for data processing particularly useful in combining convolutions of the spreading code, scrambling code and channel response in order to construct a system transmission coefficient matrix, while maintaining the same circuit size and execution time relative to performing each convolution separately. One register for processing real channel response values and a second register for processing imaginary channel response values, are used for moving channel responses through the convolution. In place of multipliers, an optimized minimum number of adders connected in a pyramid configuration are used to perform the necessary multiplication of the codes, for simplicity of construction. By including the channel code transformation from binary representation to complex representation as part of the overall method, unnecessary adders are eliminated from the apparatus.
摘要翻译：一种用于数据处理的装置和方法，在组合扩展码，扰码和信道响应的卷积时特别有用，以构建系统传输系数矩阵，同时分别相对于执行每个卷积保持相同的电路大小和执行时间。用于处理实际信道响应值的一个寄存器和用于处理虚信道响应值的第二寄存器用于通过卷积移动信道响应。代替乘法器，为了简化构造，使用以金字塔配置连接的优化的最小加法器数量来执行代码的必要乘法。通过将来自二进制表示的信道码变换作为整体方法的一部分进行复杂表示，从设备中消除不必要的加法器。

4. 发明授权

US06792032B2 CDMA system transmission matrix coefficient calculation 失效
标题翻译： CDMA系统传输矩阵系数计算
公开(公告)号：US06792032B2
公开(公告)日：2004-09-14
申请号：US10040994
申请日：2001-12-28
申请人： Ryan Samuel Buchert , Chayil Timmerman , Peter Edward Becker , Muhammad Usman Fazili
发明人： Ryan Samuel Buchert , Chayil Timmerman , Peter Edward Becker , Muhammad Usman Fazili
IPC分类号： H04K100
CPC分类号： H04B1/7093 , H04B2201/70707
摘要： An apparatus and method for data processing particularly useful in combining convolutions of the spreading code, scrambling code and channel response in order to construct a system transmission coefficient matrix, while maintaining the same circuit size and execution time relative to performing each convolution separately. One register for processing real channel response values and a second register for processing imaginary channel response values, are used for moving channel responses through the convolution. In place of multipliers, an optimized minimum number of adders connected in a pyramid configuration are used to perform the necessary multiplication of the codes, for simplicity of construction. By including the channel code transformation from binary representation to complex representation as part of the overall method, unnecessary adders are eliminated from the apparatus.
摘要翻译：一种用于数据处理的装置和方法，在组合扩展码，扰码和信道响应的卷积时特别有用，以构建系统传输系数矩阵，同时分别相对于执行每个卷积保持相同的电路大小和执行时间。用于处理实际信道响应值的一个寄存器和用于处理虚信道响应值的第二寄存器用于通过卷积移动信道响应。代替乘法器，为了简化构造，使用以金字塔配置连接的优化的最小加法器数量来执行代码的必要乘法。通过将来自二进制表示的信道码变换作为整体方法的一部分进行复杂表示，从设备中消除不必要的加法器。

5. 发明申请

US20090190645A1 ADVANCED RECEIVER WITH SLIDING WINDOW BLOCK LINEAR EQUALIZER 审中-公开
标题翻译：具有滑动窗框线性均衡器的先进接收器
公开(公告)号：US20090190645A1
公开(公告)日：2009-07-30
申请号：US12419333
申请日：2009-04-07
申请人： Bin Li , Robert A. DiFazio , Jung-Lin Pan , Alexander Reznik , John David Kaewell, JR. , Peter Edward Becker
发明人： Bin Li , Robert A. DiFazio , Jung-Lin Pan , Alexander Reznik , John David Kaewell, JR. , Peter Edward Becker
IPC分类号： H04L25/49 , H03H7/30
CPC分类号： H04L25/03159 , H04B17/336
摘要： A receiver or an integrated circuit (IC) incorporated therein includes a fast Fourier transform (FFT)-based (or hybrid FFT-based) sliding window block level equalizer (BLE) for generating equalized samples. The BLE includes a noise power estimator, first and second channel estimators, an FFT-based chip level equalizer (CLEQ) and a channel monitor unit. The noise power estimator generates a noise power estimate based on two diverse sample data streams. The channel estimators generate respective channel estimates based on the sample data streams. The channel monitor unit generates a first channel monitor signal including truncated channel estimate vectors based on the channel estimates, and a second channel monitor signal which indicates an approximate rate of change of the truncated channel estimate vectors. The FFT-based CLEQ generates the equalized samples based on the noise power estimate, one-block samples of the first and second sample data streams, the channel estimates and the monitor signals.
摘要翻译：结合在其中的接收器或集成电路（IC）包括用于产生均衡样本的基于快速傅立叶变换（FFT）（或基于混合FFT）的滑动窗口块级均衡器（BLE）。 BLE包括噪声功率估计器，第一和第二信道估计器，基于FFT的码片级均衡器（CLEQ）和信道监视器单元。噪声功率估计器基于两个不同的采样数据流产生噪声功率估计。信道估计器基于样本数据流生成相应的信道估计。信道监视单元基于信道估计产生包括截断的信道估计向量的第一信道监视信号，以及指示截断的信道估计向量的近似变化率的第二信道监视信号。基于FFT的CLEQ基于噪声功率估计，第一和第二采样数据流的一个块采样，信道估计和监视信号来生成均衡的采样。

6. 发明授权

US07570689B2 Advanced receiver with sliding window block linear equalizer 失效
标题翻译：高级接收机带滑动窗口线性均衡器
公开(公告)号：US07570689B2
公开(公告)日：2009-08-04
申请号：US11238318
申请日：2005-09-29
申请人： Bin Li , Robert A. DiFazio , Jung-Lin Pan , Alexander Reznik , John David Kaewell, Jr. , Peter Edward Becker
发明人： Bin Li , Robert A. DiFazio , Jung-Lin Pan , Alexander Reznik , John David Kaewell, Jr. , Peter Edward Becker
IPC分类号： H04L25/49 , H04L27/04 , H03H7/30
CPC分类号： H04L25/03159 , H04B17/336
摘要： A receiver or an integrated circuit (IC) incorporated therein includes a fast Fourier transform (FFT)-based (or hybrid FFT-based) sliding window block level equalizer (BLE) for generating equalized samples. The BLE includes a noise power estimator, first and second channel estimators, an FFT-based chip level equalizer (CLEQ) and a channel monitor unit. The noise power estimator generates a noise power estimate based on two diverse sample data streams. The channel estimators generate respective channel estimates based on the sample data streams. The channel monitor unit generates a first channel monitor signal including truncated channel estimate vectors based on the channel estimates, and a second channel monitor signal which indicates an approximate rate of change of the truncated channel estimate vectors. The FFT-based CLEQ generates the equalized samples based on the noise power estimate, one-block samples of the first and second sample data streams, the channel estimates and the monitor signals.
摘要翻译：结合在其中的接收器或集成电路（IC）包括用于产生均衡样本的基于快速傅立叶变换（FFT）（或基于混合FFT）的滑动窗口块级均衡器（BLE）。 BLE包括噪声功率估计器，第一和第二信道估计器，基于FFT的码片级均衡器（CLEQ）和信道监视器单元。噪声功率估计器基于两个不同的采样数据流产生噪声功率估计。信道估计器基于样本数据流生成相应的信道估计。信道监视单元基于信道估计产生包括截断的信道估计向量的第一信道监视信号，以及指示截断的信道估计向量的近似变化率的第二信道监视信号。基于FFT的CLEQ基于噪声功率估计，第一和第二采样数据流的一个块采样，信道估计和监视信号来生成均衡的采样。

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