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1. 发明授权

US08020168B2 Dynamic virtual software pipelining on a network on chip 失效
标题翻译：在芯片上的动态虚拟软件流水线
公开(公告)号：US08020168B2
公开(公告)日：2011-09-13
申请号：US12117897
申请日：2008-05-09
申请人： Russell D. Hoover , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
发明人： Russell D. Hoover , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
IPC分类号： G06F15/76 , G06F9/46
CPC分类号： G06F15/17356 , G06F15/7825
摘要： A NOC for dynamic virtual software pipelining including IP blocks, routers, memory communications controllers, and network interface controllers, each IP block adapted to a router through a memory communications controller and a network interface controller, the NOC also including: a computer software application segmented into stages, each stage comprising a flexibly configurable module of computer program instructions identified by a stage ID, each stage assigned to a thread of execution on an IP block; and each stage executing on a thread of execution on an IP block, including a first stage executing on an IP block, producing output data and sending by the first stage the produced output data to a second stage, the output data including control information for the next stage and payload data; and the second stage consuming the produced output data in dependence upon the control information.
摘要翻译：一种用于动态虚拟软件流水线的NOC，包括IP块，路由器，存储器通信控制器和网络接口控制器，每个IP块通过存储器通信控制器和网络接口控制器适配于路由器，NOC还包括：计算机软件应用程序分段每个阶段包括由阶段ID标识的计算机程序指令的灵活可配置模块，每个阶段分配给IP块上的执行线程; 并且每个阶段在IP块上执行的执行线程，包括在IP块上执行的第一阶段，产生输出数据，并且通过第一阶段将产生的输出数据发送到第二阶段，所述输出数据包括用于下一阶段和有效载荷数据; 并且第二阶段根据控制信息消耗所产生的输出数据。

2. 发明申请

US20090282222A1 Dynamic Virtual Software Pipelining On A Network On Chip 失效
标题翻译：网络上的动态虚拟软件流水线
公开(公告)号：US20090282222A1
公开(公告)日：2009-11-12
申请号：US12117897
申请日：2008-05-09
申请人： Russell D. Hoover , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
发明人： Russell D. Hoover , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
IPC分类号： G06F9/30
CPC分类号： G06F15/17356 , G06F15/7825
摘要： A NOC for dynamic virtual software pipelining including IP blocks, routers, memory communications controllers, and network interface controllers, each IP block adapted to a router through a memory communications controller and a network interface controller, the NOC also including: a computer software application segmented into stages, each stage comprising a flexibly configurable module of computer program instructions identified by a stage ID, each stage assigned to a thread of execution on an IP block; and each stage executing on a thread of execution on an IP block, including a first stage executing on an IP block, producing output data and sending by the first stage the produced output data to a second stage, the output data including control information for the next stage and payload data; and the second stage consuming the produced output data in dependence upon the control information.
摘要翻译：一种用于动态虚拟软件流水线的NOC，包括IP块，路由器，存储器通信控制器和网络接口控制器，每个IP块通过存储器通信控制器和网络接口控制器适配于路由器，NOC还包括：计算机软件应用程序分段每个阶段包括由阶段ID标识的计算机程序指令的灵活可配置模块，每个阶段分配给IP块上的执行线程; 并且每个阶段在IP块上执行的执行线程，包括在IP块上执行的第一阶段，产生输出数据，并且通过第一阶段将产生的输出数据发送到第二阶段，所述输出数据包括用于下一阶段和有效载荷数据; 并且第二阶段根据控制信息消耗所产生的输出数据。

3. 发明申请

US20090138567A1 Network on chip with partitions 失效
标题翻译：网络芯片与分区
公开(公告)号：US20090138567A1
公开(公告)日：2009-05-28
申请号：US12102038
申请日：2008-04-14
申请人： Russell D. Hoover , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
发明人： Russell D. Hoover , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
IPC分类号： G06F15/167
CPC分类号： G06F15/16
摘要： A design structure embodied in a machine readable medium is provided. Embodiments of the design structure include a network on chip (‘NOC’), the NOC comprising: integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controller, each IP block adapted to a router through a memory communications controller and a network interface controller, each memory communications controller controlling communication between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers; the network organized into partitions, each partition including at least one IP block, each partition assigned exclusive access to a separate physical memory address space; and one or more applications executing on one or more of the partitions.
摘要翻译：提供体现在机器可读介质中的设计结构。该设计结构的实施例包括片上网络（NOC），NOC包括：集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器，每个IP块通过存储器适配于路由器通信控制器和网络接口控制器，每个存储器通信控制器控制IP块和存储器之间的通信，以及每个网络接口控制器通过路由器控制IP间块通信; 网络组织成分区，每个分区包括至少一个IP块，每个分区分配独占访问单独的物理内存地址空间; 以及在一个或多个分区上执行的一个或多个应用程序。

4. 发明授权

US07873701B2 Network on chip with partitions 失效
标题翻译：网络芯片与分区
公开(公告)号：US07873701B2
公开(公告)日：2011-01-18
申请号：US12102038
申请日：2008-04-14
申请人： Russell D. Hoover , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
发明人： Russell D. Hoover , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
IPC分类号： G06F15/16
CPC分类号： G06F15/16
摘要： A design structure embodied in a machine readable medium is provided. Embodiments of the design structure include a network on chip (‘NOC’), the NOC comprising: integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controller, each IP block adapted to a router through a memory communications controller and a network interface controller, each memory communications controller controlling communication between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers; the network organized into partitions, each partition including at least one IP block, each partition assigned exclusive access to a separate physical memory address space; and one or more applications executing on one or more of the partitions.
摘要翻译：提供体现在机器可读介质中的设计结构。该设计结构的实施例包括片上网络（NOC），NOC包括：集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器，每个IP块通过存储器适配于路由器通信控制器和网络接口控制器，每个存储器通信控制器控制IP块和存储器之间的通信，以及控制通过路由器进行IP间块通信的每个网络接口控制器; 网络组织成分区，每个分区包括至少一个IP块，每个分区分配独占访问单独的物理内存地址空间; 以及在一个或多个分区上执行的一个或多个应用程序。

5. 发明申请

US20090282226A1 Context Switching On A Network On Chip 有权
标题翻译：上下文切换网络芯片
公开(公告)号：US20090282226A1
公开(公告)日：2009-11-12
申请号：US12118039
申请日：2008-05-09
申请人： Russell D. Hoover , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
发明人： Russell D. Hoover , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
IPC分类号： G06F9/30
CPC分类号： G06F15/7825 , H04L49/109
摘要： A network on chip (‘NOC’) that includes IP blocks, routers, memory communications controllers, and network interface controllers, each IP block adapted to the network by an application messaging interconnect including an inbox and an outbox, one or more of the IP blocks including computer processors supporting a plurality of threads, the NOC also including an inbox and outbox controller configured to set pointers to the inbox and outbox, respectively, that identify valid message data for a current thread; and software running in the current thread that, upon a context switch to a new thread, is configured to: save the pointer values for the current thread, and reset the pointer values to identify valid message data for the new thread, where the inbox and outbox controller are further configured to retain the valid message data for the current thread in the boxes until context switches again to the current thread.
摘要翻译：包括IP块，路由器，存储器通信控制器和网络接口控制器的片上网络（“NOC”），每个IP块通过包括收件箱和发件箱的应用消息传送互连网络适配到网络，IP网络中的一个或多个块，包括支持多个线程的计算机处理器，NOC还包括分别设置指向当前线程的有效消息数据的收件箱和发送箱的指针的收件箱和发件箱控制器; 以及在当前线程中运行的软件，在上下文切换到新线程时，配置为：保存当前线程的指针值，并重置指针值以识别新线程的有效消息数据，其中收件箱和发送箱控制器被进一步配置为将当前线程的有效消息数据保留在框中，直到上下文再次切换到当前线程。

6. 发明申请

US20090135739A1 Network On Chip With Partitions 有权
标题翻译：网络片上分区
公开(公告)号：US20090135739A1
公开(公告)日：2009-05-28
申请号：US11945396
申请日：2007-11-27
申请人： Russell D. Hoover , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
发明人： Russell D. Hoover , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
IPC分类号： H04L12/28
CPC分类号： G06F15/7825 , H04L49/109 , H04L49/15 , H04L49/1546 , H04L49/3036 , H04L49/45
摘要： A network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, with each IP block adapted to a router through a memory communications controller and a network interface controller, where each memory communications controller controlling communications between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, with the network organized into partitions, each partition including at least one IP block, each partition assigned exclusive access to a separate physical memory address space and one or more applications executing on one or more of the partitions.
摘要翻译：包括集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器的片上网络（“NOC”），每个IP块通过存储器通信控制器和网络接口控制器适配于路由器，其中每个存储器通信控制器控制IP块和存储器之间的通信，以及控制通过路由器的IP间块通信的每个网络接口控制器，其中网络被组织成分区，每个分区包括至少一个IP块，每个分区被分配独占访问单独的物理内存地址空间和在一个或多个分区上执行的一个或多个应用程序。

7. 发明授权

US08018466B2 Graphics rendering on a network on chip 失效
标题翻译：片上网络上的图形渲染
公开(公告)号：US08018466B2
公开(公告)日：2011-09-13
申请号：US12029647
申请日：2008-02-12
申请人： Russell D. Hoover , Jamie R. Kuesel , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
发明人： Russell D. Hoover , Jamie R. Kuesel , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
IPC分类号： G09G5/00 , G06F15/16 , G06F13/14
CPC分类号： G06T1/20
摘要： Graphics rendering on a network on chip (‘NOC’) including receiving, in the geometry processor, a representation of an object to be rendered; converting, by the geometry processor, the representation of the object to two dimensional primitives; sending, by the geometry processor, the primitives to the plurality of scan converters; converting, by the scan converters, the primitives to fragments, each fragment comprising one or more portions of a pixel; for each fragment: selecting, by the scan converter for the fragment in dependence upon sorting rules, a pixel processor to process the fragment; sending, by the scan converter to the pixel processor, the fragment; and processing, by the pixel processor, the fragment to produce pixels for an image.
摘要翻译：包括在芯片上的图形渲染（“NOC”），包括在几何处理器中接收要呈现的对象的表示; 通过几何处理器将对象的表示转换成二维原语; 由所述几何处理器将所述原语发送到所述多个扫描转换器; 由扫描转换器将原语转换成片段，每个片段包括像素的一个或多个部分; 对于每个片段：由扫描转换器根据排序规则选择片段以处理片段的像素处理器; 由扫描转换器向像素处理器发送片段; 以及由所述像素处理器处理所述片段以产生用于图像的像素。

8. 发明申请

US20090282211A1 Network On Chip With Partitions 审中-公开
标题翻译：网络片上分区
公开(公告)号：US20090282211A1
公开(公告)日：2009-11-12
申请号：US12117906
申请日：2008-05-09
申请人： Russell D. Hoover , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
发明人： Russell D. Hoover , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
IPC分类号： G06F12/02
CPC分类号： G06F12/1483 , G06F15/7825
摘要： Data processing with a network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controller, including: organizing the network into partitions; assigning all IP blocks of a partition a partition identifier (‘partition ID’) that uniquely identifies for an IP block a particular partition in which the IP block is included; establishing one or more permissions tables associating partition IDs with sources and destinations of data communications on the NOC, each record in the permissions tables representing a restriction on data communications on the NOC; executing one or more applications on one or more of the partitions, including transmitting data communications messages among IP blocks and between IP blocks and memory, each data communications message including a partition ID of a sender of the data communications message; and controlling data communications among the partitions in dependence upon the permissions tables and the partition IDs.
摘要翻译：包括集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器的片上网络（“NOC”）的数据处理，包括：将网络组织成分区; 为分区的所有IP块分配一个分区标识符（“分区ID”），其为IP块唯一地标识其中包括IP块的特定分区; 建立将分区ID与NOC上的数据通信的源和目的地相关联的一个或多个许可表，权限表中的每个记录表示对NOC上的数据通信的限制; 在一个或多个分区上执行一个或多个应用，包括在IP块之间以及IP块和存储器之间传送数据通信消息，每个数据通信消息包括数据通信消息的发送者的分区ID; 以及根据权限表和分区ID控制分区之间的数据通信。

9. 发明申请

US20090282227A1 Monitoring Software Pipeline Performance On A Network On Chip 失效
标题翻译：监控网络芯片上的软件流水线性能
公开(公告)号：US20090282227A1
公开(公告)日：2009-11-12
申请号：US12117875
申请日：2008-05-09
申请人： Russell D. Hoover , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
发明人： Russell D. Hoover , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
IPC分类号： G06F9/30
CPC分类号： G06F11/3404 , G06F15/7825
摘要： Software pipelining on a network on chip (‘NOC’), the NOC including integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, each IP block adapted to a router through a memory communications controller and a network interface controller, each memory communications controller controlling communication between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers. Embodiments of the present invention include implementing a software pipeline on the NOC, including segmenting a computer software application into stages, each stage comprising a flexibly configurable module of computer program instructions identified by a stage ID; executing each stage of the software pipeline on a thread of execution on an IP block; monitoring software pipeline performance in real time; and reconfiguring the software pipeline, dynamically, in real time, and in dependence upon the monitored software pipeline performance.
摘要翻译：芯片上的软件流水线（NOC），NOC包括集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器，每个IP块通过存储器通信控制器和路由器网络接口控制器，每个存储器通信控制器控制IP块和存储器之间的通信，以及控制通过路由器进行IP间块通信的每个网络接口控制器。本发明的实施例包括在NOC上实现软件管线，包括将计算机软件应用程序分阶段分段，每个阶段包括由阶段ID标识的计算机程序指令的灵活可配置模块; 在IP块上执行一个执行线程的软件流水线的每个阶段; 实时监控软件流水线性能; 并且动态地，实时地重新配置软件流水线，并且依赖于监视的软件流水线性能。

10. 发明授权

US08526422B2 Network on chip with partitions 有权
标题翻译：网络芯片与分区
公开(公告)号：US08526422B2
公开(公告)日：2013-09-03
申请号：US11945396
申请日：2007-11-27
申请人： Russell D. Hoover , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
发明人： Russell D. Hoover , Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
IPC分类号： H04L12/28
CPC分类号： G06F15/7825 , H04L49/109 , H04L49/15 , H04L49/1546 , H04L49/3036 , H04L49/45
摘要： A network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, with each IP block adapted to a router through a memory communications controller and a network interface controller, where each memory communications controller controlling communications between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, with the network organized into partitions, each partition including at least one IP block, each partition assigned exclusive access to a separate physical memory address space and one or more applications executing on one or more of the partitions.
摘要翻译：包括集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器的片上网络（“NOC”），每个IP块通过存储器通信控制器和网络接口控制器适配于路由器，其中每个存储器通信控制器控制IP块和存储器之间的通信，以及控制通过路由器的IP间块通信的每个网络接口控制器，其中网络被组织成分区，每个分区包括至少一个IP块，每个分区被分配独占访问单独的物理内存地址空间和在一个或多个分区上执行的一个或多个应用程序。

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