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    • 3. 发明授权
    • Array communications arrangement for parallel processor
    • 并行处理器的阵列通信布置
    • US5152000A
    • 1992-09-29
    • US478082
    • 1990-02-09
    • Daniel W. Hillis
    • Daniel W. Hillis
    • G06F15/173G06F15/80
    • G06F15/17381G06F15/8023G06F15/803
    • A chip array comprising a plurality of integrated circuit chips. Each chip comprises a plurality of processors, each processor including a data generation circuit for generating data and data receiving circuit for receiving data, a plurality of on-chip links for interconnecting the processors on each chip to form a processor array on the chip to facilitate the parallel transfer of data generated by the processors along selected directions in the processor array during a parallel data transfer operation, and a plurality of sets of selectively-energizable data transfer terminals. Each set of the data transfer terminals facilitates the transfer of data transmitted by processors along an edge of the processor array defined on the chip, between chips along a selected direction in the chip array during the parallel data transfer operation, with at least one set of data transfer terminals facilitating the transfer of data along at least two non-collinear directions in the chip array. A plurality of communications links connected between sets of data transfer terminals of respective chips interconnect the chips to form the chip array. The communications links that are connected to the "one set of data transfer terminals" of each chip are connected to sets of data transfer terminals of each of at least two other chips along at least two non-collinear directions in the chip array to selectively facilitate the transfer of data therethrough with at least two other chips during the parallel data transfer operation.
    • 一种芯片阵列,包括多个集成电路芯片。 每个芯片包括多个处理器,每个处理器包括用于产生用于接收数据的数据和数据接收电路的数据产生电路,用于互连每个芯片上的处理器的多个片上链路,以在芯片上形成处理器阵列以便于 在并行数据传送操作期间由处理器沿着所选方向在处理器阵列中并行传输数据,以及多组选择性激励的数据传输终端。 每组数据传输终端有助于在并行数据传输操作期间沿芯片阵列中选定的方向在芯片之间沿着芯片上定义的处理器阵列的边缘传输的数据传输到至少一组 数据传输终端便于沿芯片阵列中的至少两个非共线方向传输数据。 连接在各个芯片的数据传送终端的组之间的多个通信链路互连芯片以形成芯片阵列。 连接到每个芯片的“一组数据传输终端”的通信链路沿着芯片阵列中的至少两个非共线方向连接到至少两个其他芯片中的每一个的数据传输终端的集合,以选择性地促进 在并行数据传输操作期间使用至少两个其他芯片传送数据。