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1. 发明授权

US6165863A Aluminum-filled self-aligned trench for stacked capacitor structure and methods 失效
公开(公告)号：US6165863A
公开(公告)日：2000-12-26
申请号：US102331
申请日：1998-06-22
申请人： Ruojia Lee , Ralph Kauffman , J. Dennis Keller
发明人： Ruojia Lee , Ralph Kauffman , J. Dennis Keller
IPC分类号： H01L21/02 , H01L21/285 , H01L21/60 , H01L21/8242 , H01L27/108 , H01L21/20
CPC分类号： H01L27/10888 , H01L21/28518 , H01L21/76897 , H01L21/823425 , H01L21/823475 , H01L27/10811 , H01L28/91
摘要： An aluminum interconnect which extends adjacent to and is insulated from a stacked capacitor structure to facilitate electrical communication between an active device region of a semiconductor substrate of a semiconductor device structure and a bit line extending above the semiconductor substrate. The aluminum interconnect is disposed within a trench and may include a metal silicide layer adjacent the active device region to form a buried metal diffusion layer. The aluminum interconnect may also include a metal nitride layer disposed between the metal silicide and aluminum. The invention also includes methods of fabricating aluminum interconnects adjacent stacked capacitor structures and semiconductor device structures which include the aluminum interconnects.

2. 发明授权

US07057285B2 Aluminum interconnects with metal silicide diffusion barriers 失效
标题翻译：铝与金属硅化物扩散阻挡层互连
公开(公告)号：US07057285B2
公开(公告)日：2006-06-06
申请号：US10931181
申请日：2004-08-30
申请人： Ruojia Lee , Ralph Kauffman , J. Dennis Keller
发明人： Ruojia Lee , Ralph Kauffman , J. Dennis Keller
IPC分类号： H01L21/20
CPC分类号： H01L27/10888 , H01L21/28518 , H01L21/76897 , H01L21/823425 , H01L21/823475 , H01L27/10811 , H01L28/91
摘要： An aluminum interconnect which extends adjacent to and is insulated from a stacked capacitor structure to facilitate electrical communication between an active device region of a semiconductor substrate of a semiconductor device structure and a bit line extending above the semiconductor substrate. The aluminum interconnect is disposed within a trench and may include a metal silicide layer adjacent the active device region to form a buried metal diffusion layer. The aluminum interconnect may also include a metal nitride layer disposed between the metal silicide and aluminum. The invention also includes methods of fabricating aluminum interconnects adjacent stacked capacitor structures and semiconductor device structures which include the aluminum interconnects.
摘要翻译：一个铝互连件，其与堆叠的电容器结构相邻延伸并且与堆叠的电容器结构绝缘，以促进半导体器件结构的半导体衬底的有源器件区域与在半导体衬底之上延伸的位线之间的电连通。铝互连件设置在沟槽内，并且可以包括邻近有源器件区域的金属硅化物层以形成掩埋的金属扩散层。铝互连还可以包括设置在金属硅化物和铝之间的金属氮化物层。本发明还包括制造邻近叠层电容器结构的铝互连和包括铝互连的半导体器件结构的方法。

3. 发明授权

US06787428B2 Aluminum-filled self-aligned trench for stacked capacitor structure and methods 失效
公开(公告)号：US06787428B2
公开(公告)日：2004-09-07
申请号：US10180846
申请日：2002-06-26
申请人： Ruojia Lee , Ralph Kauffman , J. Dennis Keller
发明人： Ruojia Lee , Ralph Kauffman , J. Dennis Keller
IPC分类号： H01L2120
CPC分类号： H01L27/10888 , H01L21/28518 , H01L21/76897 , H01L21/823425 , H01L21/823475 , H01L27/10811 , H01L28/91
摘要： An aluminum interconnect which extends adjacent to and is insulated from a stacked capacitor structure to facilitate electrical communication between an active device region of a semiconductor substrate of a semiconductor device structure and a bit line extending above the semiconductor substrate. The aluminum interconnect is disposed within a trench and may include a metal silicide layer adjacent the active device region to form a buried metal diffusion layer. The aluminum interconnect may also include a metal nitride layer disposed between the metal silicide and aluminum. The invention also includes methods of fabricating aluminum interconnects adjacent stacked capacitor structures and semiconductor device structures which include the aluminum interconnects.

4. 发明授权

US06720605B1 Aluminum-filled self-aligned trench for stacked capacitor structure and methods 失效
标题翻译：用于堆叠电容器的铝填充自对准沟槽结构和方法
公开(公告)号：US06720605B1
公开(公告)日：2004-04-13
申请号：US09651879
申请日：2000-08-29
申请人： Ruojia Lee , Ralph Kauffman , J. Dennis Keller
发明人： Ruojia Lee , Ralph Kauffman , J. Dennis Keller
IPC分类号： H01L27108
CPC分类号： H01L27/10888 , H01L21/28518 , H01L21/76897 , H01L21/823425 , H01L21/823475 , H01L27/10811 , H01L28/91
摘要： An aluminum interconnect which extends adjacent to and is insulated from a stacked capacitor structure to facilitate electrical communication between an active device region of a semiconductor substrate of a semiconductor device structure and a bit line extending above the semiconductor substrate. The aluminum interconnect is disposed within a trench and may include a metal silicide layer adjacent the active device region to form a buried metal diffusion layer. The aluminum interconnect may also include a metal nitride layer disposed between the metal silicide and aluminum. The invention also includes methods of fabricating aluminum interconnects adjacent stacked capacitor structures and semiconductor device structures which include the aluminum interconnects.
摘要翻译：一个铝互连件，其与堆叠的电容器结构相邻延伸并且与堆叠的电容器结构绝缘，以促进半导体器件结构的半导体衬底的有源器件区域与在半导体衬底之上延伸的位线之间的电连通。铝互连件设置在沟槽内，并且可以包括邻近有源器件区域的金属硅化物层以形成掩埋的金属扩散层。铝互连还可以包括设置在金属硅化物和铝之间的金属氮化物层。本发明还包括制造邻近叠层电容器结构的铝互连和包括铝互连的半导体器件结构的方法。

5. 发明授权

US06465319B1 Aluminum-filled self-aligned trench for stacked capacitor structure and methods 失效
标题翻译：用于堆叠电容器的铝填充自对准沟槽结构和方法
公开(公告)号：US06465319B1
公开(公告)日：2002-10-15
申请号：US09651384
申请日：2000-08-29
申请人： Ruojia Lee , Ralph Kauffman , J. Dennis Keller
发明人： Ruojia Lee , Ralph Kauffman , J. Dennis Keller
IPC分类号： H01L2120
CPC分类号： H01L27/10888 , H01L21/28518 , H01L21/76897 , H01L21/823425 , H01L21/823475 , H01L27/10811 , H01L28/91
摘要： An aluminum interconnect which extends adjacent to and is insulated from a stacked capacitor structure to facilitate electrical communication between an active device region of a semiconductor substrate of a semiconductor device structure and a bit line extending above the semiconductor substrate. The aluminum interconnect is disposed within a trench and may include a metal silicide layer adjacent the active device region to form a buried metal diffusion layer. The aluminum interconnect may also include a metal nitride layer disposed between the metal silicide and aluminum. The invention also includes methods of fabricating aluminium interconnects adjacent stacked capacitor structures and semiconductor device structures which include the aluminum interconnects.
摘要翻译：一个铝互连件，其与堆叠的电容器结构相邻延伸并且与堆叠的电容器结构绝缘，以促进半导体器件结构的半导体衬底的有源器件区域与在半导体衬底之上延伸的位线之间的电连通。铝互连件设置在沟槽内，并且可以包括邻近有源器件区域的金属硅化物层以形成掩埋的金属扩散层。铝互连还可以包括设置在金属硅化物和铝之间的金属氮化物层。本发明还包括制造邻近叠层电容器结构的铝互连和包括铝互连的半导体器件结构的方法。

6. 发明授权

US5292681A Method of processing a semiconductor wafer to form an array of nonvolatile memory devices employing floating gate transistors and peripheral area having CMOS transistors 失效
标题翻译：处理半导体晶片以形成采用浮置晶体管和具有CMOS晶体管的外围区域的非易失性存储器件阵列的方法
公开(公告)号：US5292681A
公开(公告)日：1994-03-08
申请号：US123611
申请日：1993-09-16
申请人： Roger R. Lee , Tyler A. Lowrey , Fernando Gonzalez , J. Dennis Keller
发明人： Roger R. Lee , Tyler A. Lowrey , Fernando Gonzalez , J. Dennis Keller
IPC分类号： H01L21/8247 , H01L27/105 , H01L21/266
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11546
摘要： Disclosed is fabricating a semiconductor wafer to form a memory array and peripheral area, the array comprising nonvolatile memory devices employing floating gate transistors and the peripheral area comprising CMOS transistors. A first layer of conductive material is applied atop insulating layers. A dielectric layer is applied atop the first conductive layer for use in floating gate transistors within the array. The dielectric layer and first conductive material are etched from the peripheral area, leaving patterned dielectric material and first conductive material in the array. A second layer of conductive material is applied atop the wafer to cover the peripheral area and dielectric layer of the array. The conductive and dielectric materials of the array are patterned and etched separately from the patterning and etching of conductive material of each of the first and second conductivity type CMOS transistors of the peripheral area. As well, the conductive material of the first conductivity type CMOS transistors of the peripheral area are patterned and etched separately from the patterning and etching of each of, a) conductive and dielectric materials of the array, and b) conductive material of the second conductivity type CMOS transistors of the peripheral area. Further, the conductive material of the second conductivity type CMOS transistors of the peripheral area are patterned and etched separately from patterning and etching of each of, a) conductive and dielectric materials of the array, and b) conductive material of the first conductivity type CMOS transistors of the peripheral area.
摘要翻译：公开了制造半导体晶片以形成存储器阵列和外围区域，该阵列包括采用浮置栅极晶体管的非易失性存储器件以及包含CMOS晶体管的外围区域。将第一层导电材料施加在绝缘层上。将电介质层施加在第一导电层顶上，用于阵列内的浮栅晶体管。电介质层和第一导电材料从周边区域被蚀刻，留下图案化的介电材料和第一导电材料在阵列中。将第二层导电材料施加在晶片顶部以覆盖阵列的外围区域和电介质层。与周边区域的第一和第二导电型CMOS晶体管的导电材料的图案化和蚀刻分开地对阵列的导电和介电材料进行图案化和蚀刻。同样地，外围区域的第一导电型CMOS晶体管的导电材料被图案化和蚀刻与阵列的a）导电和介电材料的图案化和蚀刻分开，以及b）第二导电性的导电材料型CMOS晶体管。此外，外围区域的第二导电类型CMOS晶体管的导电材料被图案化和蚀刻与阵列的a）导电和介电材料的图案化和蚀刻分开，以及b）第一导电类型CMOS的导电材料外围区域的晶体管。

7. 发明授权

US07192829B2 Methods of forming floating gate transistors 失效
标题翻译：形成浮栅晶体管的方法
公开(公告)号：US07192829B2
公开(公告)日：2007-03-20
申请号：US09118359
申请日：1998-07-17
申请人： J. Dennis Keller , Roger R. Lee
发明人： J. Dennis Keller , Roger R. Lee
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/4925
摘要： Floating gate transistors and methods of forming the same are described. In one implementation, a floating gate is formed over a substrate. The floating gate has an inner first portion and an outer second portion. Conductivity enhancing impurity is provided in the inner first portion to a greater concentration than conductivity enhancing impurity in the outer second portion. In another implementation, the floating gate is formed from a first layer of conductively doped semiconductive material and a second layer of substantially undoped semiconductive material. In another implementation, the floating gate is formed from a first material having a first average grain size and a second material having a second average grain size which is larger than the first average grain size.
摘要翻译：描述了浮栅晶体管及其形成方法。在一个实施方式中，在衬底上形成浮栅。浮动门具有内部第一部分和外部第二部分。在内部第一部分中提供增强电导的杂质以比外部第二部分中的增强电导率的杂质更大的浓度。在另一实施方案中，浮栅由第一导电掺杂半导体材料层和基本上未掺杂的半导体材料的第二层形成。在另一实施方案中，浮栅由具有第一平均晶粒尺寸的第一材料和具有大于第一平均晶粒尺寸的第二平均晶粒尺寸的第二材料形成。

8. 发明授权

US5726471A Programmable non-volatile memory cell and method of forming a programmable non-volatile memory cell 失效
标题翻译：可编程非易失性存储器单元和形成可编程非易失性存储单元的方法
公开(公告)号：US5726471A
公开(公告)日：1998-03-10
申请号：US743503
申请日：1996-11-04
申请人： J. Dennis Keller , Roger R. Lee
发明人： J. Dennis Keller , Roger R. Lee
IPC分类号： H01L21/336 , H01L23/552 , H01L23/58 , H01L29/423 , H01L29/792
CPC分类号： H01L23/552 , H01L23/585 , H01L29/42324 , H01L29/66825 , H01L2924/0002
摘要： A method of reducing undesired electron depletion through sidewalls of a floating gate of a floating gate transistor comprising providing a non-oxide or oxynitride layer over said sidewalls. Integrated circuitry including a non-volatile field effect transistor includes, a) a floating gate transistor having a gate construction and a pair of opposing source/drain regions, the gate construction having at least one sidewall; b) a shielding layer over the gate sidewall; and c) a dielectric layer on the shielding layer, the dielectric layer being of a different material than the shielding layer. The shielding layer might be provided over an oxide layer previously provided on sidewalls of the gate construction. The shielding layer might be provided over sidewall spacers previously provided relative to sidewalls of the gate construction. Example and preferred shielding layer materials include Si.sub.3 N.sub.4, oxynitride compounds, and aluminum.
摘要翻译：一种通过浮置栅极晶体管的浮置栅极的侧壁减少不需要的电子耗尽的方法，包括在所述侧壁上提供非氧化物或氧氮化物层。包括非易失性场效应晶体管的集成电路包括：a）具有栅极结构和一对相对的源极/漏极区域的浮栅晶体管，栅极结构具有至少一个侧壁; b）栅极侧壁上的屏蔽层; 以及c）所述屏蔽层上的电介质层，所述电介质层的材料与所述屏蔽层不同。屏蔽层可以设置在预先设置在栅极结构的侧壁上的氧化物层上。屏蔽层可以设置在先前相对于栅极结构的侧壁提供的侧壁间隔壁上。示例性和优选的屏蔽层材料包括Si 3 N 4，氮氧化合物和铝。

9. 发明授权

US06791141B1 Semiconductor constructions comprising stacks with floating gates therein 失效
标题翻译：半导体结构包括其中具有浮动栅极的堆叠
公开(公告)号：US06791141B1
公开(公告)日：2004-09-14
申请号：US09172096
申请日：1998-10-13
申请人： J. Dennis Keller , Roger R. Lee
发明人： J. Dennis Keller , Roger R. Lee
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/4925
摘要： Floating gate transistors and methods of forming the same are described. In one implementation, a floating gate is formed over a substrate. The floating gate has an inner first portion and an outer second portion. Conductivity enhancing impurity is provided in the inner first portion to a greater concentration than conductivity enhancing impurity in the outer second portion. In another implementation, the floating gate is formed from a first layer of conductively doped semiconductive material and a second layer of substantially undoped semiconductive material. In another implementation, the floating gate is formed from a first material having a first average grain size and a second material having a second average grain size which is larger than the first average grain size.
摘要翻译：描述了浮栅晶体管及其形成方法。在一个实施方式中，在衬底上形成浮栅。浮动门具有内部第一部分和外部第二部分。在内部第一部分中提供增强电导的杂质以比外部第二部分中的增强电导率的杂质更大的浓度。在另一实施方案中，浮栅由第一导电掺杂半导体材料层和基本上未掺杂的半导体材料的第二层形成。在另一实施方案中，浮栅由具有第一平均晶粒尺寸的第一材料和具有大于第一平均晶粒尺寸的第二平均晶粒尺寸的第二材料形成。

10. 发明授权

US5985719A Method of forming a programmable non-volatile memory cell 失效
标题翻译：形成可编程非易失性存储单元的方法
公开(公告)号：US5985719A
公开(公告)日：1999-11-16
申请号：US977313
申请日：1997-11-24
申请人： J. Dennis Keller , Roger R. Lee
发明人： J. Dennis Keller , Roger R. Lee
IPC分类号： H01L21/336 , H01L23/552 , H01L23/58 , H01L29/423 , H01L21/8247
CPC分类号： H01L23/552 , H01L23/585 , H01L29/42324 , H01L29/66825 , H01L2924/0002
摘要： A method of reducing undesired electron depletion through sidewalls of a floating gate of a floating gate transistor comprising providing a non-oxide or oxynitride layer over said sidewalls. Integrated circuitry including a non-volatile field effect transistor includes, a) a floating gate transistor having a gate construction and a pair of opposing source/drain regions, the gate construction having at least one sidewall; b) a shielding layer over the gate sidewall; and c) a dielectric layer on the shielding layer, the dielectric layer being of a different material than the shielding layer. The shielding layer might be provided over an oxide layer previously provided on sidewalls of the gate construction. The shielding layer might be provided over sidewall spacers previously provided relative to sidewalls of the gate construction. Example and preferred shielding layer materials include Si.sub.3 N.sub.4, oxynitride compounds, and aluminum.
摘要翻译：一种通过浮置栅极晶体管的浮置栅极的侧壁减少不需要的电子耗尽的方法，包括在所述侧壁上提供非氧化物或氧氮化物层。包括非易失性场效应晶体管的集成电路包括：a）具有栅极结构和一对相对的源极/漏极区域的浮栅晶体管，栅极结构具有至少一个侧壁; b）栅极侧壁上的屏蔽层; 以及c）所述屏蔽层上的电介质层，所述电介质层的材料与所述屏蔽层不同。屏蔽层可以设置在预先设置在栅极结构的侧壁上的氧化物层上。屏蔽层可以设置在先前相对于栅极结构的侧壁提供的侧壁间隔壁上。示例性和优选的屏蔽层材料包括Si 3 N 4，氮氧化合物和铝。

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