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1. 发明授权

US07554832B2 Passive element memory array incorporating reversible polarity word line and bit line decoders 有权
标题翻译：无源元件存储阵列，包含可逆极性字线和位线解码器
公开(公告)号：US07554832B2
公开(公告)日：2009-06-30
申请号：US11461339
申请日：2006-07-31
申请人： Luca G. Fasoli , Christopher J. Petti , Roy E. Scheuerlein
发明人： Luca G. Fasoli , Christopher J. Petti , Roy E. Scheuerlein
IPC分类号： G11C11/00
CPC分类号： G11C8/14
摘要： Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more thane one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.
摘要翻译：描述了用于解码可编程的示例性存储器阵列的电路和方法，在一些实施例中，可重写无源元件存储器单元，其对于具有多于一个存储器平面的非常密集的三维存储器阵列特别有用。此外，描述了用于选择这种存储器阵列的一个或多个阵列块的电路和方法，用于选择所选择的阵列块内的一个或多个字线和位线，用于将数据信息传送到选定的阵列块内的选定的存储器单元并且用于将未选择的偏置条件传送到未选择的阵列块。

2. 发明申请

US20080025066A1 PASSIVE ELEMENT MEMORY ARRAY INCORPORATING REVERSIBLE POLARITY WORD LINE AND BIT LINE DECODERS 有权
标题翻译：被动元素存储阵列引入可反转的极性字线和位线解码器
公开(公告)号：US20080025066A1
公开(公告)日：2008-01-31
申请号：US11461339
申请日：2006-07-31
申请人： Luca G. Fasoli , Christopher J. Petti , Roy E. Scheuerlein
发明人： Luca G. Fasoli , Christopher J. Petti , Roy E. Scheuerlein
IPC分类号： G11C11/00
CPC分类号： G11C8/14
摘要： Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more thane one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.
摘要翻译：描述了用于解码可编程的示例性存储器阵列的电路和方法，在一些实施例中，可重写无源元件存储器单元，其对于具有多于一个存储器平面的非常密集的三维存储器阵列特别有用。此外，描述了用于选择这种存储器阵列的一个或多个阵列块的电路和方法，用于选择所选择的阵列块内的一个或多个字线和位线，用于将数据信息传送到选定的阵列块内的选定的存储器单元并且用于将未选择的偏置条件传送到未选择的阵列块。

3. 发明授权

US07463546B2 Method for using a passive element memory array incorporating reversible polarity word line and bit line decoders 有权
标题翻译：使用包含可逆极性字线和位线解码器的无源元件存储器阵列的方法
公开(公告)号：US07463546B2
公开(公告)日：2008-12-09
申请号：US11461364
申请日：2006-07-31
申请人： Luca G. Fasoli , Christopher J. Petti , Roy E. Scheuerlein
发明人： Luca G. Fasoli , Christopher J. Petti , Roy E. Scheuerlein
IPC分类号： G11C8/00
CPC分类号： G11C17/18 , G11C8/08 , G11C8/10 , G11C17/16 , G11C17/165
摘要： Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.
摘要翻译：描述了用于解码可编程的示例性存储器阵列的电路和方法，在一些实施例中，可重写无源元件存储器单元，其对于具有多于一个存储器平面的非常密集的三维存储器阵列特别有用。此外，描述了用于选择这种存储器阵列的一个或多个阵列块的电路和方法，用于选择所选择的阵列块内的一个或多个字线和位线，用于将数据信息传送到选定的阵列块内的选定的存储器单元并且用于将未选择的偏置条件传送到未选择的阵列块。

4. 发明申请

US20080025134A1 METHOD FOR USING TWO DATA BUSSES FOR MEMORY ARRAY BLOCK SELECTION 有权
标题翻译：使用两个数据总线进行存储器阵列选择的方法
公开(公告)号：US20080025134A1
公开(公告)日：2008-01-31
申请号：US11461372
申请日：2006-07-31
申请人： Roy E. Scheuerlein , Luca G. Fasoli , Christopher J. Petti
发明人： Roy E. Scheuerlein , Luca G. Fasoli , Christopher J. Petti
IPC分类号： G11C11/00 , G11C7/10 , G11C8/00
CPC分类号： G11C8/14 , G11C7/1048 , G11C7/18 , G11C8/08 , G11C8/12
摘要： Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.
摘要翻译：描述了用于解码可编程的示例性存储器阵列的电路和方法，在一些实施例中，可重写无源元件存储器单元，其对于具有多于一个存储器平面的非常密集的三维存储器阵列特别有用。此外，描述了用于选择这种存储器阵列的一个或多个阵列块的电路和方法，用于选择所选择的阵列块内的一个或多个字线和位线，用于将数据信息传送到选定的阵列块内的选定的存储器单元并且用于将未选择的偏置条件传送到未选择的阵列块。

5. 发明授权

US07463536B2 Memory array incorporating two data busses for memory array block selection 有权
标题翻译：包含两个数据总线的存储器阵列用于存储器阵列块选择
公开(公告)号：US07463536B2
公开(公告)日：2008-12-09
申请号：US11461359
申请日：2006-07-31
申请人： Roy E. Scheuerlein , Luca G. Fasoli , Christopher J. Petti
发明人： Roy E. Scheuerlein , Luca G. Fasoli , Christopher J. Petti
IPC分类号： G11C8/12
CPC分类号： G11C17/18 , G11C5/063 , G11C7/1048 , G11C7/12 , G11C7/18 , G11C8/08 , G11C8/10 , G11C8/12 , G11C8/14
摘要： Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.
摘要翻译：描述了用于解码可编程的示例性存储器阵列的电路和方法，在一些实施例中，可重写无源元件存储器单元，其对于具有多于一个存储器平面的非常密集的三维存储器阵列特别有用。此外，描述了用于选择这种存储器阵列的一个或多个阵列块的电路和方法，用于选择所选择的阵列块内的一个或多个字线和位线，用于将数据信息传送到选定的阵列块内的选定的存储器单元并且用于将未选择的偏置条件传送到未选择的阵列块。

6. 发明申请

US20080025085A1 MEMORY ARRAY INCORPORATING TWO DATA BUSSES FOR MEMORY ARRAY BLOCK SELECTION 有权
标题翻译：内存阵列，用于存储阵列选择两个数据总线
公开(公告)号：US20080025085A1
公开(公告)日：2008-01-31
申请号：US11461359
申请日：2006-07-31
申请人： Roy E. Scheuerlein , Luca G. Fasoli , Christopher J. Petti
发明人： Roy E. Scheuerlein , Luca G. Fasoli , Christopher J. Petti
IPC分类号： G11C16/04
CPC分类号： G11C17/18 , G11C5/063 , G11C7/1048 , G11C7/12 , G11C7/18 , G11C8/08 , G11C8/10 , G11C8/12 , G11C8/14
摘要： Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.
摘要翻译：描述了用于解码可编程的示例性存储器阵列的电路和方法，在一些实施例中，可重写无源元件存储器单元，其对于具有多于一个存储器平面的非常密集的三维存储器阵列特别有用。此外，描述了用于选择这种存储器阵列的一个或多个阵列块的电路和方法，用于选择所选择的阵列块内的一个或多个字线和位线，用于将数据信息传送到选定的阵列块内的选定的存储器单元并且用于将未选择的偏置条件传送到未选择的阵列块。

7. 发明申请

US20080025132A1 METHOD FOR USING A PASSIVE ELEMENT MEMORY ARRAY INCORPORATING REVERSIBLE POLARITY WORD LINE AND BIT LINE DECODERS 有权
标题翻译：使用无源元件存储器阵列的方法，包含可反映的极性字线和位线解码器
公开(公告)号：US20080025132A1
公开(公告)日：2008-01-31
申请号：US11461364
申请日：2006-07-31
申请人： Luca G. Fasoli , Christopher J. Petti , Roy E. Scheuerlein
发明人： Luca G. Fasoli , Christopher J. Petti , Roy E. Scheuerlein
IPC分类号： G11C11/00 , G11C8/00
CPC分类号： G11C17/18 , G11C8/08 , G11C8/10 , G11C17/16 , G11C17/165
摘要： Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.
摘要翻译：描述了用于解码可编程的示例性存储器阵列的电路和方法，在一些实施例中，可重写无源元件存储器单元，其对于具有多于一个存储器平面的非常密集的三维存储器阵列特别有用。此外，描述了用于选择这种存储器阵列的一个或多个阵列块的电路和方法，用于选择所选择的阵列块内的一个或多个字线和位线，用于将数据信息传送到选定的阵列块内的选定的存储器单元并且用于将未选择的偏置条件传送到未选择的阵列块。

8. 发明授权

US07570523B2 Method for using two data busses for memory array block selection 有权
标题翻译：使用两个数据总线进行存储器阵列块选择的方法
公开(公告)号：US07570523B2
公开(公告)日：2009-08-04
申请号：US11461372
申请日：2006-07-31
申请人： Roy E. Scheuerlein , Luca G. Fasoli , Christopher J. Petti
发明人： Roy E. Scheuerlein , Luca G. Fasoli , Christopher J. Petti
IPC分类号： G11C11/00
CPC分类号： G11C8/14 , G11C7/1048 , G11C7/18 , G11C8/08 , G11C8/12
摘要： Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.
摘要翻译：描述了用于解码可编程的示例性存储器阵列的电路和方法，在一些实施例中，可重写无源元件存储器单元，其对于具有多于一个存储器平面的非常密集的三维存储器阵列特别有用。此外，描述了用于选择这种存储器阵列的一个或多个阵列块的电路和方法，用于选择所选择的阵列块内的一个或多个字线和位线，用于将数据信息传送到选定的阵列块内的选定的存储器单元并且用于将未选择的偏置条件传送到未选择的阵列块。

9. 发明授权

US07272052B2 Decoding circuit for non-binary groups of memory line drivers 有权
标题翻译：用于非二进制组的存储器线路驱动器的解码电路
公开(公告)号：US07272052B2
公开(公告)日：2007-09-18
申请号：US11146952
申请日：2005-06-07
申请人： Roy E. Scheuerlein , Christopher J. Petti , Luca G. Fasoli
发明人： Roy E. Scheuerlein , Christopher J. Petti , Luca G. Fasoli
IPC分类号： G11C16/06
CPC分类号： G11C8/10 , G11C5/063 , G11C8/08 , G11C8/14
摘要： A decoding circuit for non-binary groups of memory line drivers is disclosed. In one embodiment, an integrated circuit is disclosed comprising a binary decoder and circuitry operative to perform a non-binary arithmetic operation, wherein a result of the non-binary arithmetic operation is provided as input to the binary decoder. In another embodiment, an integrated circuit is disclosed comprising a memory array comprising a plurality of array lines, a non-integral-power-of-two number of array line driver circuits, and control circuitry configured to select one of the array line driver circuits. The control circuitry can comprise a binary decoder and a pre-decoder portion that performs a non-binary arithmetic operation. The concepts described herein may be used alone or in combination.
摘要翻译：公开了一种用于非二进制组的存储器线驱动器的解码电路。在一个实施例中，公开了一种集成电路，其包括二进制解码器和用于执行非二进制算术运算的电路，其中非二进制算术运算的结果被提供作为二进制解码器的输入。在另一个实施例中，公开了一种集成电路，其包括存储器阵列，该存储器阵列包括多个阵列线，两个非整数倍数量的阵列线驱动器电路，以及控制电路，被配置为选择阵列线驱动电路之一。控制电路可以包括执行非二进制算术运算的二进制解码器和预解码器部分。本文所述的概念可以单独使用或组合使用。

10. 发明授权

US08809128B2 Methods and apparatus for layout of three dimensional matrix array memory for reduced cost patterning 有权
标题翻译：用于三维矩阵阵列存储器布局的方法和装置，用于降低成本图案化
公开(公告)号：US08809128B2
公开(公告)日：2014-08-19
申请号：US12911900
申请日：2010-10-26
申请人： Roy E. Scheuerlein , Christopher J. Petti , Yoichiro Tanaka
发明人： Roy E. Scheuerlein , Christopher J. Petti , Yoichiro Tanaka
IPC分类号： H01L21/82 , H01L27/24
CPC分类号： G11C5/06 , H01L21/0337 , H01L27/0207 , H01L27/0688 , H01L27/101 , H01L27/2481 , H01L2924/0002 , Y10S257/909 , H01L2924/00
摘要： The present invention provides apparatus, methods, and systems for a memory layer layout for a three-dimensional memory. The memory layer includes a plurality of memory array blocks; a plurality of memory lines coupled to the memory array blocks; and a plurality of zia contact areas for coupling the memory layer to other memory layers in a three-dimensional memory. The memory lines extend from the memory array blocks and are formed using a sidewall defined process. The memory lines have a half pitch dimension smaller than the nominal minimum feature size capability of a lithography tool used in forming the memory lines. The zia contact areas have a dimension that is approximately four times the half pitch dimension of the memory lines. The memory lines are arranged in a pattern adapted to allow a single memory line to intersect a single zia contact area and to provide area between other memory lines for other zia contact areas. Numerous additional aspects are disclosed.
摘要翻译：本发明提供了一种用于三维存储器的存储器层布局的装置，方法和系统。存储层包括多个存储器阵列块; 耦合到所述存储器阵列块的多个存储线; 以及用于将存储器层耦合到三维存储器中的其它存储器层的多个zia接触区域。存储器线从存储器阵列块延伸并且使用侧壁限定的工艺形成。存储器线具有小于用于形成存储器线的光刻工具的标称最小特征尺寸能力的半间距尺寸。 zia接触区域的尺寸约为存储器线的半间距尺寸的四倍。存储线被布置成适于允许单个存储器线与单个zia接触区域相交并且为其它zia接触区域提供其它存储器线路之间的区域的图案。公开了许多附加方面。

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