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1. 发明授权

US07694205B2 Method and apparatus for providing a read channel having combined parity and non-parity post processing 有权
标题翻译：用于提供具有组合奇偶校验和非奇偶校验后处理的读通道的方法和装置
公开(公告)号：US07694205B2
公开(公告)日：2010-04-06
申请号：US11067851
申请日：2005-02-28
申请人： Roy D. Cideciyan , Ajay Dholakia , Evangelos S. Eleftheriou , Richard L. Galbraith , Weldon M. Hanson , Thomas Mittelholzer , Travis R. Oenning
发明人： Roy D. Cideciyan , Ajay Dholakia , Evangelos S. Eleftheriou , Richard L. Galbraith , Weldon M. Hanson , Thomas Mittelholzer , Travis R. Oenning
IPC分类号： G11C29/00 , H03M13/00
CPC分类号： H03M13/45 , G11B20/10009 , G11B20/10055 , G11B20/1833 , G11B2020/1863 , H03M13/098 , H03M13/6343
摘要： A method and apparatus for providing a read channel having combined parity and non-parity post processing is disclosed. A post-processor combines parity and non-parity post processing to make both parity and non-parity corrections so that error events that cannot be detected by parity may be corrected. Non-parity detectable error events are only kept for consideration if their likelihood is above a set threshold.
摘要翻译：公开了一种用于提供具有组合奇偶校验和非奇偶校验后处理的读通道的方法和装置。后处理器组合奇偶校验和非奇偶校验后处理以进行奇偶校验和非奇偶校正，从而校正不能被奇偶校验检测到的错误事件。只有当它们的可能性高于设定的阈值时，才能保持非奇偶校验可检测误差事件。

2. 发明授权

US08276038B2 Data storage systems 有权
标题翻译：数据存储系统
公开(公告)号：US08276038B2
公开(公告)日：2012-09-25
申请号：US11833274
申请日：2007-08-03
申请人： Roy D. Cideciyan , Ajay Dholakia , Evangelos S. Eleftheriou , Richard L. Galbraith , Weldon M. Hanson , Thomas Mittelholzer , Travis R. Oenning
发明人： Roy D. Cideciyan , Ajay Dholakia , Evangelos S. Eleftheriou , Richard L. Galbraith , Weldon M. Hanson , Thomas Mittelholzer , Travis R. Oenning
IPC分类号： H03M7/46 , H03M13/03 , G11B20/18
CPC分类号： H03M5/145 , G11B20/1833 , G11B2020/1836 , H03M13/15 , H03M13/1515 , H03M13/27 , H03M13/6343
摘要： A data storage system includes an encoder subsystem comprising an error correction code encoder, a modulation encoder, and a precoder, and a decoder subsystem similarly comprising a detector, an inverse precoder, a channel decoder, and an error correction code decoder. The error correction encoder applies an error correction code to the incoming user bit stream, and the modulation encoder applies so-called modulation or constrained coding to the error correction coded bit stream. The precoder applies so-called preceding to the modulation encoded bit stream. However, this preceding is applied to selected portions of the bit stream only. There can also be a permutation step where the bit sequence is permuted after the modulation encoder before preceding is applied by the precoder. The decoder subsystem operates in the inverse manner.
摘要翻译：数据存储系统包括编码器子系统，包括纠错码编码器，调制编码器和预编码器，以及类似地包括检测器，逆预编码器，信道解码器和纠错码解码器的解码器子系统。误差校正编码器对输入用户比特流应用纠错码，并且调制编码器将所谓的调制或约束编码应用于纠错编码比特流。预编码器将所谓的前面应用于调制编码比特流。然而，上述内容仅适用于位流的选定部分。还可以存在一个置换步骤，其中比特序列在调制编码器之前被预编码器施加之前被置换。解码器子系统以相反的方式运行。

3. 发明申请

US20090089645A1 DATA STORAGE SYSTEMS 审中-公开
标题翻译：数据存储系统
公开(公告)号：US20090089645A1
公开(公告)日：2009-04-02
申请号：US12058151
申请日：2008-03-28
申请人： Roy D. Cideciyan , Ajay Dholakia , Evangelos S. Eleftheriou , Thomas Mittelholzer
发明人： Roy D. Cideciyan , Ajay Dholakia , Evangelos S. Eleftheriou , Thomas Mittelholzer
IPC分类号： H03M13/00
CPC分类号： G11B20/1833
摘要： Method and apparatus for decoding data in a data storage system. In operation, a detector generates an output bit stream in dependence on a data block received from a storage subsystem of the data storage system. A post processor connected to the detector generates a first error corrected bit stream in dependence on the output bit stream and the data block. An error correction decoder connected to the post processor generates a second error corrected bit stream in dependence on the first error corrected bit stream and also generates a checksum in dependence of the second error corrected bit stream. A feedback path supplies from the error correction decoder to the post processor pinning data indicative of locations of correct bits in the second error corrected bit stream in the event that the checksum is indicative of errors in the second error corrected bit stream and the second error corrected bit stream comprises at least one correct interleave. The post processor regenerates the first error corrected bit stream in dependence on the pinning data received from the error correction decoder.
摘要翻译：用于在数据存储系统中解码数据的方法和装置。在操作中，检测器根据从数据存储系统的存储子系统接收的数据块产生输出位流。连接到检测器的后处理器根据输出比特流和数据块生成第一纠错比特流。连接到后处理器的纠错解码器根据第一纠错比特流产生第二纠错比特流，并且还根据第二纠错比特流产生校验和。在校验和指示第二纠错比特流中的错误并且校正的第二错误的情况下，反馈路径从错误校正解码器向后处理器提供钉扎指示第二纠错比特流中的正确比特的位置的数据位流包括至少一个正确的交错。后处理器根据从纠错解码器接收到的钉扎数据重新生成第一纠错比特流。

4. 发明授权

US07395482B2 Data storage systems 有权
标题翻译：数据存储系统
公开(公告)号：US07395482B2
公开(公告)日：2008-07-01
申请号：US10739966
申请日：2003-12-18
申请人： Roy D. Cideciyan , Ajay Dholakia , Evangelos S. Eleftheriou , Richard L. Galbraith , Weldon M. Hanson , Thomas Mittelholzer , Travis R. Oenning
发明人： Roy D. Cideciyan , Ajay Dholakia , Evangelos S. Eleftheriou , Richard L. Galbraith , Weldon M. Hanson , Thomas Mittelholzer , Travis R. Oenning
IPC分类号： H03M13/00
CPC分类号： G11B20/1833
摘要： A data storage system includes an encoder subsystem comprising an error correction code encoder, a modulation encoder, and a precoder, and a decoder subsystem similarly comprising a detector, an inverse precoder, a channel decoder, and an error correction code decoder. The error correction encoder applies an error correction code to the incoming user bit stream, and the modulation encoder applies so-called modulation or constrained coding to the error correction coded bit stream. The precoder applies so-called precoding to the modulation encoded bit stream. However, this precoding is applied to selected portions of the bit stream only. There can also be a permutation step where the bit sequence is permuted after the modulation encoder before precoding is applied by the precoder. The decoder subsystem operates in the inverse manner.
摘要翻译：数据存储系统包括编码器子系统，包括纠错码编码器，调制编码器和预编码器，以及类似地包括检测器，逆预编码器，调制解码器和纠错码解码器的解码器子系统。误差校正编码器对输入用户比特流应用纠错码，并且调制编码器将所谓的调制或约束编码应用于纠错编码比特流。预编码器将所谓的预编码应用于调制编码比特流。然而，该预编码仅应用于位流的选定部分。还可以存在一个置换步骤，其中在由预编码器施加预编码之前，该位序列在调制编码器之后被置换。解码器子系统以相反的方式运行。

5. 发明授权

US07193802B2 Apparatus for providing dynamic equalizer optimization 失效
标题翻译：用于提供动态均衡器优化的装置
公开(公告)号：US07193802B2
公开(公告)日：2007-03-20
申请号：US10809230
申请日：2004-03-25
申请人： Roy D. Cideciyan , Ajay Dholakia , Evangelos S. Eleftheriou , Richard L. Galbraith , Weldon M. Hanson , Thomas Mittelholzer , Travis R. Oenning , Michael J. Ross , David J. Stanek
发明人： Roy D. Cideciyan , Ajay Dholakia , Evangelos S. Eleftheriou , Richard L. Galbraith , Weldon M. Hanson , Thomas Mittelholzer , Travis R. Oenning , Michael J. Ross , David J. Stanek
IPC分类号： G11B5/09 , G11B5/035 , H03K5/139
CPC分类号： G11B5/035
摘要： An apparatus for providing dynamic equalizer optimization is disclosed. The present invention solves the above-described problems by providing equalizer coefficient updates that converge towards the same solution as the direct method without having to first write a known pattern to the disk or requiring any prior knowledge of the data already written on the disk. The adaptive cosine function may be used to modify only a DFIR tap set, only the j and k parameters of a cosine equalizer or to modify both the tap set for a DFIR filter and the j and k parameters of the cosine equalizer. Another algorithm, such as the LMS algorithm, may be used to modify parameters not modified by the cosine algorithm.
摘要翻译：公开了一种用于提供动态均衡器优化的装置。本发明通过提供均衡器系数更新来解决上述问题，所述均衡器系数更新收敛于与直接方法相同的解决方案，而不必首先将已知模式写入盘或需要任何已经写入盘中的数据的任何知识。自适应余弦函数可用于仅修改DFIR抽头集，仅修改余弦均衡器的j和k参数，或者修改DFIR滤波器的抽头集合和余弦均衡器的j和k参数。可以使用诸如LMS算法的另一种算法来修改未被余弦算法修改的参数。

6. 发明授权

US07574646B2 Data storage systems 失效
标题翻译：数据存储系统
公开(公告)号：US07574646B2
公开(公告)日：2009-08-11
申请号：US11286582
申请日：2005-11-25
申请人： Roy D. Cideciyan , Ajay Dholakia , Evangelos S. Eleftheriou , Thomas Mittelholzer
发明人： Roy D. Cideciyan , Ajay Dholakia , Evangelos S. Eleftheriou , Thomas Mittelholzer
IPC分类号： H03M13/00
CPC分类号： G11B20/1833
摘要： A method for decoding data in a data storage system includes generating an output bit stream; generating a first error corrected bit stream in dependence on the output bit stream; generating a second error corrected bit stream in dependence on the first error corrected bit stream; generating a checksum in dependence of the second error corrected bit stream; and, in the event that the checksum is indicative of errors in the second error corrected bit stream and the second error corrected bit stream comprises at least one correct interleave: supplying data indicative of locations of correct bits in the second error corrected bit stream; and, regenerating the first error corrected bit stream in dependence on the pinning data.
摘要翻译：一种用于在数据存储系统中解码数据的方法包括：生成输出比特流; 根据输出比特流产生第一纠错比特流; 根据第一纠错比特流产生第二纠错比特流; 根据第二纠错比特流产生校验和; 并且在所述校验和指示所述第二纠错比特流中的错误并且所述第二纠错比特流包括至少一个正确交错的情况下：提供指示所述第二纠错比特流中的正确比特的位置的数据; 以及根据钉扎数据再生第一纠错比特流。

7. 发明申请

US20090027242A1 HIGH-RATE RLL ENCODING 有权
标题翻译：高速RLL编码
公开(公告)号：US20090027242A1
公开(公告)日：2009-01-29
申请号：US12185095
申请日：2008-08-03
申请人： Roy D. Cideciyan , Evangelos S. Eleftheriou , Thomas Mittelholzer , Paul J. Seger , Keisuke Tanaka
发明人： Roy D. Cideciyan , Evangelos S. Eleftheriou , Thomas Mittelholzer , Paul J. Seger , Keisuke Tanaka
IPC分类号： H03M7/00
CPC分类号： H03M5/145 , G11B20/1426 , G11B2020/1446 , G11B2020/1473 , G11B2220/90 , G11B2220/956
摘要： An unencoded m-bit data input sequence is divided into a block of n bits and a block of m-n bits. The block of n bits is divided into a first set of n+1 encoded bits, wherein at least one of P1 subblocks of the first set satisfies a G, M and I constraints. The first set of n+1 encoded bits is mapped into a second set of n+1 encoded bits wherein at least one of P2 subblocks of the second set gives rise to at least Q1 transitions after 1/(1+D2) precoding. A second set of n+1 encoded bits is divided into P3 encoded subblocks and the P3 encoded subblocks are interleaved among (m−n)/s unencoded symbols so as to form a (m+1)-bit output sequence codeword which is then stored on a data storage medium.
摘要翻译：未编码的m位数据输入序列被分成n位块和m-n位块。 n位的块被划分为第一组n + 1个编码比特，其中第一组的P1个子块中的至少一个满足G，M和I约束。第一组n + 1个编码比特被映射到n + 1编码比特的第二组，其中第二组的P2子块中的至少一个在1 /（1 + D2）预编码之后产生至少Q1个转换。第二组n + 1编码比特被分成P3编码子块，并且P3编码子块在（mn）/ s个未编码符号之间进行交织，以形成第（m + 1）比特的输出序列码字，然后存储在数据存储介质。

8. 发明授权

US08930798B2 Data encoding in solid state storage devices 有权
标题翻译：固态存储设备中的数据编码
公开(公告)号：US08930798B2
公开(公告)日：2015-01-06
申请号：US13582768
申请日：2011-03-23
申请人： Roy D. Cideciyan , Evangelos S. Eleftheriou , Thomas Mittelholzer
发明人： Roy D. Cideciyan , Evangelos S. Eleftheriou , Thomas Mittelholzer
IPC分类号： H03M13/00 , H03M13/29 , H03M13/15 , G06F11/10
CPC分类号： H03M13/2906 , G06F11/1072 , H03M13/152 , H03M13/2942
摘要： Methods and apparatus are provided for encoding input data for recording in s-level storage of a solid state storage device, where s f 2. Input data words are encoded in groups of M input data words in accordance with first and second BCH codes to produce, for each group, a set of M first codewords of the first BCH code. The set of M first codewords is produced such that at least one predetermined linear combination of the M first codewords produces a second codeword of the second BCH code, this second BCH code being a sub-code of the first BCH code. The sets of M first codewords are then recorded in the s-level storage. If each of the first and second codewords comprises N q-ary symbols where q=pk, k is a positive integer and p is a prime number, the q-ary code alphabet can be matched to the s-ary storage by ensuring that q and s are uth and vth powers respectively of a common base r, where u and v are positive integers and k f u, whereby p(k/u)v=s.
摘要翻译：提供了用于编码用于在固态存储设备的s级存储中记录的输入数据的方法和装置，其中sf 2.根据第一和第二BCH码，输入数据字以M个输入数据字的组进行编码，对于每个组，第一BCH码的一组M个第一码字。产生M个第一码字集合，使得M个第一码字的至少一个预定线性组合产生第二BCH码的第二码字，该第二BCH码是第一BCH码的子码。然后将M组第一码字集合记录在s级存储器中。如果第一和第二码字中的每一个包括N q个符号，其中q = pk，k是正整数，p是质数，则可以通过确保q- 和s分别是公共基础r的uth和vth权力，其中u和v是正整数和kfu，由此p（k / u）v = s。

9. 发明授权

US08276045B2 ECC interleaving for multi-track recording on magnetic tape 有权
标题翻译：用于磁带上多轨记录的ECC交错
公开(公告)号：US08276045B2
公开(公告)日：2012-09-25
申请号：US12351738
申请日：2009-01-09
申请人： Roy D. Cideciyan , Evangelos S. Eleftheriou , Hisato Matsuo , Thomas Mittelholzer , Paul J. Seger , Keisuke Tanaka
发明人： Roy D. Cideciyan , Evangelos S. Eleftheriou , Hisato Matsuo , Thomas Mittelholzer , Paul J. Seger , Keisuke Tanaka
IPC分类号： G11C29/00
CPC分类号： H03M13/2909 , G11B20/1202 , G11B20/1833 , G11B20/1866 , G11B2020/1836 , G11B2020/1853 , G11B2220/93 , H03M13/15 , H03M13/1515
摘要： Conventional C2 coding and interleaving for multi-track data tape in LTO-3/4 do not support recording data onto a number of concurrent tracks which is not a power of two. Higher-rate longer C2 codes, which do not degrade error rate performance, are provided. An adjustable format and interleaving scheme accommodates future tape drives in which the number of concurrent tracks is not necessarily a power of two. A data set is segmented into a plurality of unencoded subdata sets and parity bytes are generated for each row and column. The parameters of the C2 code include N2 as the least common multiple of the number of possible tracks to which codeword objects are to be written. COs are formed from N2 C1 codewords, mapped onto a logical data track according to information within headers of the CO and modulation encoded into synchronized COs which are written to the tape.
摘要翻译： LTO-3/4中的多轨数据磁带的常规C2编码和交织不支持将数据记录到不是2的幂的多个并发磁道上。提供了更高速率的更长的C2代码，这不会降低错误率性能。可调格式和交错方案适应将来的磁带驱动器，其中并发轨道的数量不一定是二的幂。将数据集分割为多个未编码的子数据集，并为每行和列生成奇偶校验字节。 C2码的参数包括N2作为要写入码字对象的可能轨道数的最小公倍数。 CO由N 2 C1码字形成，根据被写入到磁带的编码到同步的CO中的CO和报头中的信息映射到逻辑数据轨道。

10. 发明授权

US07876516B2 Rewrite-efficient ECC/interleaving for multi-track recording on magnetic tape 有权
标题翻译：在磁带上进行多轨录音的高效ECC /交错
公开(公告)号：US07876516B2
公开(公告)日：2011-01-25
申请号：US12351747
申请日：2009-01-09
申请人： Roy D. Cideciyan , Evangelos S. Eleftheriou , Hisato Matsuo , Thomas Mittelholzer , Paul J. Seger , Keisuke Tanaka
发明人： Roy D. Cideciyan , Evangelos S. Eleftheriou , Hisato Matsuo , Thomas Mittelholzer , Paul J. Seger , Keisuke Tanaka
IPC分类号： G11B5/09 , G11B20/14
CPC分类号： G11B20/1833 , G11B20/1201 , G11B20/1866 , G11B2020/1287 , G11B2020/1289 , G11B2020/1446 , G11B2020/1836 , G11B2220/93 , H03M13/27 , H03M13/271
摘要： For writing data to multi-track tape, a received data set is received and segmented into unencoded subdata sets, each comprising an array having K2 rows and K1 columns. For each unencoded subdata set, N1-K1 C1-parity bytes are generated for each row and N2-K2 C2-parity bytes are generated for each column. The C1 and C2 parity bytes are appended to the ends of the row and column, respectively, to form encoded C1 and C2 codewords, respectively. All of the C1 codewords per data set are endowed with a specific codeword header to form a plurality of partial codeword objects (PCOs). Each PCO is mapped onto a logical data track according to information within the header. On each logical data track, adjacent PCOs are merged to form COs which are modulation encoded and mapped into synchronized COs. Then T synchronized COs are written simultaneously to the data tape where T is the number of concurrent active tracks on the data tape.
摘要翻译：为了将数据写入多轨磁带，接收到的数据集并被分割成未编码的子数据集，每个子集包括具有K2行和K1列的阵列。对于每个未编码的子数据集，为每行生成N1-K1 C1-奇偶校验字节，并为每列生成N2-K2 C2-奇偶校验字节。 C1和C2奇偶校验字节分别附加到行和列的末端，分别形成编码的C1和C2码字。每个数据集的所有C1码字都具有特定的码字头以形成多个部分码字对象（PCO）。每个PCO根据标题内的信息被映射到逻辑数据轨道上。在每个逻辑数据轨道上，相邻的PCO被合并以形成被调制编码并被映射到同步的CO中的CO。然后将T同步的CO同时写入数据磁带，其中T是数据磁带上的并发活动磁道的数量。

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