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1. 发明授权

US07974272B2 Remote control of a switching node in a stack of switching nodes 有权
标题翻译：交换节点堆叠中的交换节点的远程控制
公开(公告)号：US07974272B2
公开(公告)日：2011-07-05
申请号：US10901873
申请日：2004-07-29
申请人： Rong-Feng Chang , Mike Twu , Craig Barrack , Allen Yu
发明人： Rong-Feng Chang , Mike Twu , Craig Barrack , Allen Yu
IPC分类号： H04Q11/00 , H04L12/56
CPC分类号： H04L41/0803 , H04L49/555 , H04L49/557 , H04L49/65
摘要： A methods and apparatus for remote management of switching network nodes in a stack via in-band messaging are presented. Switching nodes in the stack default to reserved switching node identifiers and stacking ports default to a blocking state upon startup, restart, and reset. Each command frame received via a blocking state is forwarded to a command engine at each switching node and is acknowledged with the current switching node identifier. Each acknowledgement frame bearing the reserved network node identifier triggers configuration of the acknowledging switching node. Switching nodes and the management processor track interrupt state vectors regarding events. An interrupt acknowledgement process is employed to track raised interrupts. Configuration of switching node is performed via command frames transmitted by the management processor and destined to a command engine associated with the switching node. Services provided by the management processor are requested via control frames destined to the switching node to which the management processor is attached and destined to the management port thereof. The advantages are derived from engineered switching node deployments wherein an appropriate number of management processors, less than the number of switching nodes in the stack, are employed to provide services to corresponding switching nodes in the stack, based on processing, control, and configuration bandwidth requirements. The in-band configuration and control of the switching nodes in the stack reduce deployment, configuration, management, and maintenance overheads.
摘要翻译：提出了一种用于通过带内消息传递来对堆叠中的交换网络节点进行远程管理的方法和装置。堆叠中的交换节点默认为保留的交换节点标识符，堆叠端口在启动，重新启动和重置时默认为阻塞状态。经由阻塞状态接收的每个命令帧被转发到每个交换节点处的命令引擎，并且用当前交换节点标识符进行确认。具有保留网络节点标识符的每个确认帧触发确认交换节点的配置。交换节点和管理处理器跟踪关于事件的中断状态向量。采用中断确认过程来跟踪提升的中断。交换节点的配置通过由管理处理器发送并发往与交换节点相关联的命令引擎的命令帧来执行。由管理处理器提供的服务通过去往管理处理器所连接的转发节点的控制帧被请求并发往其管理端口。优点来源于工程交换节点部署，其中基于处理，控制和配置带宽，采用小于堆叠中的交换节点数量的适当数量的管理处理器来向堆栈中的相应交换节点提供服务要求。堆叠中的交换节点的带内配置和控制可以减少部署，配置，管理和维护开销。

2. 发明申请

US20060023640A1 Remote control of a switching node in a stack of switching nodes 有权
标题翻译：交换节点堆叠中的交换节点的远程控制
公开(公告)号：US20060023640A1
公开(公告)日：2006-02-02
申请号：US10901873
申请日：2004-07-29
申请人： Rong-Feng Chang , Mike Twu , Craig Barrack , Allen Yu
发明人： Rong-Feng Chang , Mike Twu , Craig Barrack , Allen Yu
IPC分类号： H04L12/28
CPC分类号： H04L41/0803 , H04L49/555 , H04L49/557 , H04L49/65
摘要： A methods and apparatus for remote management of switching network nodes in a stack via in-band messaging are presented. Switching nodes in the stack default to reserved switching node identifiers and stacking ports default to a blocking state upon startup, restart, and reset. Each command frame received via a blocking state is forwarded to a command engine at each switching node and is acknowledged with the current switching node identifier. Each acknowledgement frame bearing the reserved network node identifier triggers configuration of the acknowledging switching node. Switching nodes and the management processor track interrupt state vectors regarding events. An interrupt acknowledgement process is employed to track raised interrupts. Configuration of switching node is performed via command frames transmitted by the management processor and destined to a command engine associated with the switching node. Services provided by the management processor are requested via control frames destined to the switching node to which the management processor is attached and destined to the management port thereof. The advantages are derived from engineered switching node deployments wherein an appropriate number of management processors, less than the number of switching nodes in the stack, are employed to provide services to corresponding switching nodes in the stack, based on processing, control, and configuration bandwidth requirements. The in-band configuration and control of the switching nodes in the stack reduce deployment, configuration, management, and maintenance overheads.
摘要翻译：提出了一种用于通过带内消息传递来对堆叠中的交换网络节点进行远程管理的方法和装置。堆叠中的交换节点默认为保留的交换节点标识符，堆叠端口在启动，重新启动和重置时默认为阻塞状态。经由阻塞状态接收的每个命令帧被转发到每个交换节点处的命令引擎，并且用当前交换节点标识符进行确认。具有保留网络节点标识符的每个确认帧触发确认交换节点的配置。交换节点和管理处理器跟踪关于事件的中断状态向量。采用中断确认过程来跟踪提升的中断。交换节点的配置通过由管理处理器发送并发往与交换节点相关联的命令引擎的命令帧来执行。由管理处理器提供的服务通过去往管理处理器所连接的转发节点的控制帧被请求并发往其管理端口。优点来源于工程交换节点部署，其中基于处理，控制和配置带宽，采用小于堆叠中的交换节点数量的适当数量的管理处理器来向堆栈中的相应交换节点提供服务要求。堆叠中的交换节点的带内配置和控制可以减少部署，配置，管理和维护开销。

3. 发明申请

US20060002386A1 Combined pipelined classification and address search method and apparatus for switching environments 有权
公开(公告)号：US20060002386A1
公开(公告)日：2006-01-05
申请号：US10881226
申请日：2004-06-30
申请人： James Yik , Rong-Feng Chang , Eric Lin , John Ta , Craig Barrack
发明人： James Yik , Rong-Feng Chang , Eric Lin , John Ta , Craig Barrack
IPC分类号： H04L12/56
CPC分类号： H04L49/3063 , H04L49/201 , H04L49/602
摘要： A packet switching node having a pipelined packet processing architecture processing packets received via an input port associated with the packet switching node is presented. The method performed by the apparatus includes: determining a packet frame type of the packet received; selectively extracting packet header field values specific to a packet frame type, the extracted packet header field value including packet addressing information; ascribing to the packet a preliminary action to be performed in respect of the packet; searching packet switching information tracked by the packet switching node based on extracted packet addressing information; formulating a preliminary switch response for the packet; classifying the packet into one of a plurality of packet flows; modifying the preliminary switch response in accordance with one of the preliminary action, the packet flow into which the packet was classified, and a default port action corresponding to the input port; modifying the packet header in accordance with one of the preliminary action, the packet flow, and the default port action; and processing the packet in accordance with the switch response. Advantages are derived from: pipelined processing of packets which enables short-cutting the rest of the processing for improper packets; a flexible frame type determination which is fast for well know frame types yet flexible in support of new frame types delaying obsolescence of a particular implementation; an early determination of a processing action which is successively refined by subsequent stages; a combined Layer-2 and Layer-3 network addressing search engine operating on short bit length indexed Layer-2 and Layer-3 network addresses reducing network address table storage requirements, requiring a reduced data transfer bandwidth for network address table access, a large external hashed primary network address table, and a small internal secondary network address table; an early determination of a switch response; and packet-classification-based switch response and packet header modification.

4. 发明申请

US20060002292A1 Method and apparatus providing rapid end-to-end failover in a packet switched communications network 有权
标题翻译：在分组交换通信网络中提供快速端到端故障转移的方法和装置
公开(公告)号：US20060002292A1
公开(公告)日：2006-01-05
申请号：US10903437
申请日：2004-07-30
申请人： Rong-Feng Chang , Eric Lin , Craig Barrack
发明人： Rong-Feng Chang , Eric Lin , Craig Barrack
IPC分类号： H04L1/00
CPC分类号： H04L12/462 , H04L43/10 , H04L45/02 , H04L45/22 , H04L45/28
摘要： A hardware-based failover scheme enabling rapid end-to-end recovery is provided. Hardware logic periodically generates, transmits, receives, and processes heartbeat packets, sent from one end of the communications network to another, and then returned back. If a communications network node or communications link failure is being experienced along the transport path, then the hardware logic rapidly swaps the affected traffic conveyed to a pre-established backup transport path, typically within microseconds. Advantages are derived from the rapid failover effected end-to-end which enables continued delivery of provisioned communications services improving the resiliency and/or availability of a communications network.
摘要翻译：提供了基于硬件的故障转移方案，实现快速的端到端恢复。硬件逻辑周期性地生成，发送，接收和处理从通信网络的一端发送到另一端的心跳信息包，然后返回。如果沿着传输路径遇到通信网络节点或通信链路故障，则硬件逻辑快速地将传送到预先建立的备份传输路径的受影响的业务交换，通常在微秒内。优点来源于端对端的快速故障转移，从而能够持续提供所提供的通信服务，从而提高通信网络的弹性和/或可用性。

5. 发明授权

US07760726B2 Compact packet switching node storage architecture employing double data rate synchronous dynamic RAM 有权
标题翻译：紧凑型分组交换节点存储架构采用双倍数据速率同步动态RAM
公开(公告)号：US07760726B2
公开(公告)日：2010-07-20
申请号：US12327919
申请日：2008-12-04
申请人： Craig Barrack , Yeong Wang , Rong-Feng Chang
发明人： Craig Barrack , Yeong Wang , Rong-Feng Chang
IPC分类号： H04L12/56
CPC分类号： H04L49/352 , H04L49/103 , H04L49/109 , H04L49/90
摘要： A two-chip/single-die switch architecture and a method for accessing a DDR SDRAM memory store in a switching environment are presented. The two-chip/single-die architecture includes an internal memory storage block on the single-die, an external memory storage interface to a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), an external memory manager, and a packet data transfer engine effecting packet data transfers between an internal memory store and the external DDR SDRAM memory. The packet data transfer engine operates as an adaptation layer addressing issues related to employing appropriate: addressing schemes, granule sizes, memory transfer burst sizes, access timing, etc. The packet data transfer engine includes a minimal number of dual mode operational blocks such as: a queue manager, and adaptation receive and transmit blocks. The method relates to a packet data transfer discipline addressing random memory access latencies incurred in employing DDR SDRAM, using predictive bank switching to hide random access latencies, packet length dependent variable memory write burst lengths to minimize bank switching, and performing memory read and write operations during corresponding read and write windows. Advantages are derived from the a space-efficient two-chip/single-die switching node architecture implemented with a reduced amount of dual mode logic, and also from DDR SDRAM bandwidth utilization efficiencies.
摘要翻译：介绍了一种双芯片/单芯片开关架构和一种在交换环境中访问DDR SDRAM存储器的方法。双芯片/单芯片架构包括单芯片上的内部存储器存储块，双倍数据速率同步动态随机存取存储器（DDR SDRAM）的外部存储器存储接口，外部存储器管理器和分组数据传输引擎在内部存储器存储器和外部DDR SDRAM存储器之间影响数据包数据传输。分组数据传输引擎作为适应层来操作，以解决与采用适当的：寻址方案，粒度大小，存储器传输突发大小，访问定时等相关的问题。分组数据传输引擎包括最少数量的双模式操作模块，例如：队列管理器，以及自适应接收和发送块。该方法涉及一种分组数据传输规程，用于解决在采用DDR SDRAM时引起的随机存储器访问延迟，使用预测库切换来隐藏随机接入延迟，分组长度相关变量存储器写突发长度以最小化库切换，以及执行存储器读写操作在相应的读写窗口。优点来源于采用双模式逻辑降低的数据量以及DDR SDRAM带宽利用效率实现的节省空间的双芯片/单芯片开关节点架构。

6. 发明授权

US07486688B2 Compact packet switching node storage architecture employing Double Data Rate Synchronous Dynamic RAM 有权
标题翻译：采用双数据速率同步动态RAM的紧凑型分组交换节点存储体系结构
公开(公告)号：US07486688B2
公开(公告)日：2009-02-03
申请号：US10812141
申请日：2004-03-29
申请人： Craig Barrack , Yeong Wang , Rong-Feng Chang
发明人： Craig Barrack , Yeong Wang , Rong-Feng Chang
IPC分类号： H04L12/28
CPC分类号： H04L49/352 , H04L49/103 , H04L49/109 , H04L49/90
摘要： A two-chip/single-die switch architecture and a method for accessing a DDR SDRAM memory store in a switching environment are presented. The two-chip/single-die architecture includes an internal memory storage block on the single-die, an external memory storage interface to a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), an external memory manager, and a packet data transfer engine effecting packet data transfers between an internal memory store and the external DDR SDRAM memory. The packet data transfer engine operates as an adaptation layer addressing issues related to employing appropriate: addressing schemes, granule sizes, memory transfer burst sizes, access timing, etc. The packet data transfer engine includes a minimal number of dual mode operational blocks such as: a queue manager, and adaptation receive and transmit blocks. The method relates to a packet data transfer discipline addressing random memory access latencies incurred in employing DDR SDRAM, using predictive bank switching to hide random access latencies, packet length dependent variable memory write burst lengths to minimize bank switching, and performing memory read and write operations during corresponding read and write windows. Advantages are derived from the a space-efficient two-chip/single-die switching node architecture implemented with a reduced amount of dual mode logic, and also from DDR SDRAM bandwidth utilization efficiencies.
摘要翻译：介绍了一种双芯片/单芯片开关架构和一种在交换环境中访问DDR SDRAM存储器的方法。双芯片/单芯片架构包括单芯片上的内部存储器存储块，双倍数据速率同步动态随机存取存储器（DDR SDRAM）的外部存储器存储接口，外部存储器管理器和分组数据传输引擎在内部存储器存储器和外部DDR SDRAM存储器之间影响数据包数据传输。分组数据传输引擎作为适应层来操作，以解决与采用适当的：寻址方案，粒度大小，存储器传输突发大小，访问定时等相关的问题。分组数据传输引擎包括最少数量的双模式操作模块，例如：队列管理器，以及自适应接收和发送块。该方法涉及一种分组数据传输规程，用于解决在采用DDR SDRAM时引起的随机存储器访问延迟，使用预测库切换来隐藏随机接入延迟，分组长度相关变量存储器写突发长度以最小化库切换，以及执行存储器读写操作在相应的读写窗口。优点来源于采用双模式逻辑降低的数据量以及DDR SDRAM带宽利用效率实现的节省空间的双芯片/单芯片开关节点架构。

7. 发明授权

US07373425B2 High-speed MAC address search engine 有权
标题翻译：高速MAC地址搜索引擎
公开(公告)号：US07373425B2
公开(公告)日：2008-05-13
申请号：US10750445
申请日：2003-12-31
申请人： Craig Barrack , James Ching-Shau Yik , Rong-Feng Chang , Eric Lin
发明人： Craig Barrack , James Ching-Shau Yik , Rong-Feng Chang , Eric Lin
IPC分类号： G06F15/173 , G06F15/16
CPC分类号： H04L49/351 , H04L45/745 , H04L49/3009
摘要： Disclosed is an apparatus and method for storing and searching computer node addresses in a computer network system. In one embodiment, the apparatus comprises a frame forwarding device such as a switch. The switch includes two MAC address tables including a primary MAC address table and secondary MAC address table both for storing and searching MAC addresses. The primary table stores records that contain compressed values of MAC addresses. The records are contained in storage locations that are referenced using the compressed value of the MAC address as a search index. In order to account for searching collisions that may result from different MAC addresses compressing to the same value, each record in the primary address table is linked to a chain of records in the secondary table. The records in the secondary table store the full value of the MAC address. Each chain of records in the secondary address table contains MAC addresses the present invention.
摘要翻译：公开了一种用于在计算机网络系统中存储和搜索计算机节点地址的装置和方法。在一个实施例中，该装置包括诸如开关的帧转发装置。交换机包括两个MAC地址表，包括主MAC地址表和辅MAC地址表，用于存储和搜索MAC地址。主表存储包含MAC地址压缩值的记录。记录包含在使用MAC地址的压缩值作为搜索索引引用的存储位置。为了解决可能由不同MAC地址压缩到相同值的搜索冲突，主地址表中的每个记录链接到辅助表中的记录链。辅助表中的记录存储MAC地址的全部值。辅助地址表中的每个记录链包含本发明的MAC地址。

8. 发明申请

US20090031044A1 High-Speed MAC Address Search Engine 审中-公开
标题翻译：高速MAC地址搜索引擎
公开(公告)号：US20090031044A1
公开(公告)日：2009-01-29
申请号：US12107567
申请日：2008-04-22
申请人： Craig Barrack , James Ching-Shau Yik , Rong-Feng Chang , Eric Lin
发明人： Craig Barrack , James Ching-Shau Yik , Rong-Feng Chang , Eric Lin
IPC分类号： G06F15/16 , G06F15/173
CPC分类号： H04L49/351 , H04L45/745 , H04L49/3009
摘要： Disclosed is an apparatus and method for storing and searching computer node addresses in a computer network system. In one embodiment, the apparatus comprises a frame forwarding device such as a switch. The switch includes two MAC address tables including a primary MAC address table and secondary MAC address table both for storing and searching MAC addresses. The primary table stores records that contain compressed values of MAC addresses. The records are contained in storage locations that are referenced using the compressed value of the MAC address as a search index. In order to account for searching collisions that may result from different MAC addresses compressing to the same value, each record in the primary address table is linked to a chain of records in the secondary table. The records in the secondary table store the full value of the MAC address. Each chain of records in the secondary address table contains MAC addresses the present invention.
摘要翻译：公开了一种用于在计算机网络系统中存储和搜索计算机节点地址的装置和方法。在一个实施例中，该装置包括诸如开关的帧转发装置。交换机包括两个MAC地址表，包括主MAC地址表和辅MAC地址表，用于存储和搜索MAC地址。主表存储包含MAC地址压缩值的记录。记录包含在使用MAC地址的压缩值作为搜索索引引用的存储位置。为了解决可能由不同MAC地址压缩到相同值的搜索冲突，主地址表中的每个记录链接到辅助表中的记录链。辅助表中的记录存储MAC地址的全部值。辅助地址表中的每个记录链包含本发明的MAC地址。

9. 发明授权

US07142514B2 Bandwidth sharing using emulated weighted fair queuing 有权
公开(公告)号：US07142514B2
公开(公告)日：2006-11-28
申请号：US09808652
申请日：2001-03-15
申请人： Linghsiao Wang , Craig Barrack , Rong-Feng Chang
发明人： Linghsiao Wang , Craig Barrack , Rong-Feng Chang
IPC分类号： H04L12/26
CPC分类号： H04L47/20 , H04L47/22 , H04L47/36 , H04L47/39 , H04L47/50 , H04L47/527 , H04L47/623
摘要： A method of scheduling queue servicing in a data packet switching environment is provided. The method includes a sequence of cyclical steps. The output queues are scheduled for servicing on a least credit value basis. An output queue is selected from a group of output queues associated with a communications port. The selected output port has at least one Payload Data Unit (PDU) pending transmission and a lowest credit value associated therewith. At least one PDU having a length is transmitted from the selected output queue and the credit value is incremented taking the length of the transmitted PDU into consideration. The transmission of PDUs is divided into transmission periods. Once per transmission period credit values associated with output queues holding PDUs pending transmission are decremented in accordance with transmission apportionments assigned for each output queue. The method emulates weighted fair queue servicing with minimal computation enabling hardware implementation thereof.

10. 发明申请

US20050213571A1 Compact packet switching node storage architecture employing double data rate synchronous dynamic RAM 有权
标题翻译：紧凑型分组交换节点存储架构采用双倍数据速率同步动态RAM
公开(公告)号：US20050213571A1
公开(公告)日：2005-09-29
申请号：US10812141
申请日：2004-03-29
申请人： Craig Barrack , Yeong Wang , Rong-Feng Chang
发明人： Craig Barrack , Yeong Wang , Rong-Feng Chang
IPC分类号： H04L12/56 , H04L12/28
CPC分类号： H04L49/352 , H04L49/103 , H04L49/109 , H04L49/90
摘要： A two-chip/single-die switch architecture and a method for accessing a DDR SDRAM memory store in a switching environment are presented. The two-chip/single-die architecture includes an internal memory storage block on the single-die, an external memory storage interface to a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), an external memory manager, and a packet data transfer engine effecting packet data transfers between an internal memory store and the external DDR SDRAM memory. The packet data transfer engine operates as an adaptation layer addressing issues related to employing appropriate: addressing schemes, granule sizes, memory transfer burst sizes, access timing, etc. The packet data transfer engine includes a minimal number of dual mode operational blocks such as: a queue manager, and adaptation receive and transmit blocks. The method relates to a packet data transfer discipline addressing random memory access latencies incurred in employing DDR SDRAM, using predictive bank switching to hide random access latencies, packet length dependent variable memory write burst lengths to minimize bank switching, and performing memory read and write operations during corresponding read and write windows. Advantages are derived from the a space-efficient two-chip/single-die switching node architecture implemented with a reduced amount of dual mode logic, and also from DDR SDRAM bandwidth utilization efficiencies.
摘要翻译：介绍了一种双芯片/单芯片开关架构和一种在交换环境中访问DDR SDRAM存储器的方法。双芯片/单芯片架构包括单芯片上的内部存储器存储块，双倍数据速率同步动态随机存取存储器（DDR SDRAM）的外部存储器存储接口，外部存储器管理器和分组数据传输引擎在内部存储器存储器和外部DDR SDRAM存储器之间影响数据包数据传输。分组数据传输引擎作为适应层来操作，以解决与采用适当的：寻址方案，粒度大小，存储器传输突发大小，访问定时等相关的问题。分组数据传输引擎包括最少数量的双模式操作模块，例如：队列管理器，以及自适应接收和发送块。该方法涉及一种分组数据传输规程，用于解决在采用DDR SDRAM时引起的随机存储器访问延迟，使用预测库切换来隐藏随机接入延迟，分组长度相关变量存储器写突发长度以最小化库切换，以及执行存储器读写操作在相应的读写窗口。优点来源于采用双模式逻辑降低的数据量以及DDR SDRAM带宽利用效率实现的节省空间的双芯片/单芯片开关节点架构。

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