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1. 发明申请

US20110302395A1 HARDWARE ASSIST THREAD FOR DYNAMIC PERFORMANCE PROFILING 失效
标题翻译：用于动态性能配置的硬件辅助螺丝
公开(公告)号：US20110302395A1
公开(公告)日：2011-12-08
申请号：US12796124
申请日：2010-06-08
申请人： Ronald P. Hall , Venkat R. Indukuru , Alexander E. Mericas , Balaram Sinharoy , Zhong L. Wang
发明人： Ronald P. Hall , Venkat R. Indukuru , Alexander E. Mericas , Balaram Sinharoy , Zhong L. Wang
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/3009 , G06F9/327 , G06F11/3466 , G06F2201/865 , G06F2201/88
摘要： A method and data processing system for managing running of instructions in a program. A processor of the data processing system receives a monitoring instruction of a monitoring unit. The processor determines if at least one secondary thread of a set of secondary threads is available for use as an assist thread. The processor selects the at least one secondary thread from the set of secondary threads to become the assist thread in response to a determination that the at least one secondary thread of the set of secondary threads is available for use as an assist thread. The processor changes profiling of running of instructions in the program from the main thread to the assist thread.
摘要翻译：一种用于管理程序中的指令的运行的方法和数据处理系统。数据处理系统的处理器接收监视单元的监视指令。处理器确定一组辅助线程的至少一个辅助线程是否可用作辅助线程。响应于确定所述一组次要线程的至少一个辅助线程可用作辅助线程，所述处理器从所述辅助线程组中选择所述至少一个辅助线程以成为所述辅助线程。处理器将程序中指令的运行情况从主线程更改为辅助线程。

2. 发明授权

US08612730B2 Hardware assist thread for dynamic performance profiling 失效
标题翻译：用于动态性能分析的硬件辅助线
公开(公告)号：US08612730B2
公开(公告)日：2013-12-17
申请号：US12796124
申请日：2010-06-08
申请人： Ronald P. Hall , Venkat Rajeev Indukuru , Alexander Erik Mericas , Balaram Sinharoy , Zhong Liang Wang
发明人： Ronald P. Hall , Venkat Rajeev Indukuru , Alexander Erik Mericas , Balaram Sinharoy , Zhong Liang Wang
IPC分类号： G06F9/00
CPC分类号： G06F9/3851 , G06F9/3009 , G06F9/327 , G06F11/3466 , G06F2201/865 , G06F2201/88
摘要： A method and data processing system for managing running of instructions in a program. A processor of the data processing system receives a monitoring instruction of a monitoring unit. The processor determines if at least one secondary thread of a set of secondary threads is available for use as an assist thread. The processor selects the at least one secondary thread from the set of secondary threads to become the assist thread in response to a determination that the at least one secondary thread of the set of secondary threads is available for use as an assist thread. The processor changes profiling of running of instructions in the program from the main thread to the assist thread.
摘要翻译：一种用于管理程序中的指令的运行的方法和数据处理系统。数据处理系统的处理器接收监视单元的监视指令。处理器确定一组辅助线程的至少一个辅助线程是否可用作辅助线程。响应于确定所述一组次要线程的至少一个辅助线程可用作辅助线程，所述处理器从所述辅助线程组中选择所述至少一个辅助线程以成为所述辅助线程。处理器将程序中指令的运行情况从主线程更改为辅助线程。

3. 发明申请

US20110283095A1 Hardware Assist Thread for Increasing Code Parallelism 有权
标题翻译：硬件辅助线程增加代码并行性
公开(公告)号：US20110283095A1
公开(公告)日：2011-11-17
申请号：US12778192
申请日：2010-05-12
申请人： Ronald P. Hall , Hung Q. Le , Raul E. Silvera , Balaram Sinharoy
发明人： Ronald P. Hall , Hung Q. Le , Raul E. Silvera , Balaram Sinharoy
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3851 , G06F9/3009 , G06F9/30101 , G06F9/30149 , G06F9/30189
摘要： Mechanisms are provided for offloading a workload from a main thread to an assist thread. The mechanisms receive, in a fetch unit of a processor of the data processing system, a branch-to-assist-thread instruction of a main thread. The branch-to-assist-thread instruction informs hardware of the processor to look for an already spawned idle thread to be used as an assist thread. Hardware implemented pervasive thread control logic determines if one or more already spawned idle threads are available for use as an assist thread. The hardware implemented pervasive thread control logic selects an idle thread from the one or more already spawned idle threads if it is determined that one or more already spawned idle threads are available for use as an assist thread, to thereby provide the assist thread. In addition, the hardware implemented pervasive thread control logic offloads a portion of a workload of the main thread to the assist thread.
摘要翻译：提供了将工作负载从主线程卸载到辅助线程的机制。机构在数据处理系统的处理器的提取单元中接收主线程的分支到辅助线程指令。分支到辅助线程指令通知处理器的硬件来查找已经产生的空闲线程以用作辅助线程。硬件实现的普遍线程控制逻辑确定一个或多个已经产生的空闲线程是否可用作辅助线程。如果确定一个或多个已经产生的空闲线程可用作辅助线程，则实现的普遍线程控制逻辑的硬件从一个或多个已经产生的空闲线程中选择空闲线程，从而提供辅助线程。此外，实现的普遍线程控制逻辑的硬件将主线程的一部分工作量卸载到辅助线程。

4. 发明授权

US08423750B2 Hardware assist thread for increasing code parallelism 有权
公开(公告)号：US08423750B2
公开(公告)日：2013-04-16
申请号：US12778192
申请日：2010-05-12
申请人： Ronald P. Hall , Hung Q. Le , Raul E. Silvera , Balaram Sinharoy
发明人： Ronald P. Hall , Hung Q. Le , Raul E. Silvera , Balaram Sinharoy
IPC分类号： G06F9/48
CPC分类号： G06F9/3851 , G06F9/3009 , G06F9/30101 , G06F9/30149 , G06F9/30189
摘要： Mechanisms are provided for offloading a workload from a main thread to an assist thread. The mechanisms receive, in a fetch unit of a processor of the data processing system, a branch-to-assist-thread instruction of a main thread. The branch-to-assist-thread instruction informs hardware of the processor to look for an already spawned idle thread to be used as an assist thread. Hardware implemented pervasive thread control logic determines if one or more already spawned idle threads are available for use as an assist thread. The hardware implemented pervasive thread control logic selects an idle thread from the one or more already spawned idle threads if it is determined that one or more already spawned idle threads are available for use as an assist thread, to thereby provide the assist thread. In addition, the hardware implemented pervasive thread control logic offloads a portion of a workload of the main thread to the assist thread.

5. 发明授权

US09037837B2 Hardware assist thread for increasing code parallelism 有权
标题翻译：用于增加代码并行性的硬件辅助线程
公开(公告)号：US09037837B2
公开(公告)日：2015-05-19
申请号：US13438087
申请日：2012-04-03
申请人： Ronald P. Hall , Hung Q. Le , Raul E. Silvera , Balaram Sinharoy
发明人： Ronald P. Hall , Hung Q. Le , Raul E. Silvera , Balaram Sinharoy
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3851 , G06F9/3009 , G06F9/30101 , G06F9/30149 , G06F9/30189
摘要： Mechanisms are provided for offloading a workload from a main thread to an assist thread. The mechanisms receive, in a fetch unit of a processor of the data processing system, a branch-to-assist-thread instruction of a main thread. The branch-to-assist-thread instruction informs hardware of the processor to look for an already spawned idle thread to be used as an assist thread. Hardware implemented pervasive thread control logic determines if one or more already spawned idle threads are available for use as an assist thread. The hardware implemented pervasive thread control logic selects an idle thread from the one or more already spawned idle threads if it is determined that one or more already spawned idle threads are available for use as an assist thread, to thereby provide the assist thread. In addition, the hardware implemented pervasive thread control logic offloads a portion of a workload of the main thread to the assist thread.
摘要翻译：提供了将工作负载从主线程卸载到辅助线程的机制。机构在数据处理系统的处理器的提取单元中接收主线程的分支到辅助线程指令。分支到辅助线程指令通知处理器的硬件来查找已经产生的空闲线程以用作辅助线程。硬件实现的普遍线程控制逻辑确定一个或多个已经产生的空闲线程是否可用作辅助线程。如果确定一个或多个已经产生的空闲线程可用作辅助线程，则实现的普遍线程控制逻辑的硬件从一个或多个已经产生的空闲线程中选择空闲线程，从而提供辅助线程。此外，实现的普遍线程控制逻辑的硬件将主线程的一部分工作量卸载到辅助线程。

6. 发明申请

US20120254594A1 Hardware Assist Thread for Increasing Code Parallelism 审中-公开
标题翻译：硬件辅助线程增加代码并行性
公开(公告)号：US20120254594A1
公开(公告)日：2012-10-04
申请号：US13438087
申请日：2012-04-03
申请人： Ronald P. Hall , Hung Q. Le , Raul E. Silvera , Balaram Sinharoy
发明人： Ronald P. Hall , Hung Q. Le , Raul E. Silvera , Balaram Sinharoy
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/3009 , G06F9/30101 , G06F9/30149 , G06F9/30189
摘要： Mechanisms are provided for offloading a workload from a main thread to an assist thread. The mechanisms receive, in a fetch unit of a processor of the data processing system, a branch-to-assist-thread instruction of a main thread. The branch-to-assist-thread instruction informs hardware of the processor to look for an already spawned idle thread to be used as an assist thread. Hardware implemented pervasive thread control logic determines if one or more already spawned idle threads are available for use as an assist thread. The hardware implemented pervasive thread control logic selects an idle thread from the one or more already spawned idle threads if it is determined that one or more already spawned idle threads are available for use as an assist thread, to thereby provide the assist thread. In addition, the hardware implemented pervasive thread control logic offloads a portion of a workload of the main thread to the assist thread.
摘要翻译：提供了将工作负载从主线程卸载到辅助线程的机制。机构在数据处理系统的处理器的提取单元中接收主线程的分支到辅助线程指令。分支到辅助线程指令通知处理器的硬件来查找已经产生的空闲线程以用作辅助线程。硬件实现的普遍线程控制逻辑确定一个或多个已经产生的空闲线程是否可用作辅助线程。如果确定一个或多个已经产生的空闲线程可用作辅助线程，则实现的普遍线程控制逻辑的硬件从一个或多个已经产生的空闲线程中选择空闲线程，从而提供辅助线程。此外，实现的普遍线程控制逻辑的硬件将主线程的一部分工作量卸载到辅助线程。

7. 发明授权

US08707016B2 Thread partitioning in a multi-core environment 有权
标题翻译：多核环境中的线程分区
公开(公告)号：US08707016B2
公开(公告)日：2014-04-22
申请号：US12024211
申请日：2008-02-01
申请人： Ravi K. Arimilli , Juan C. Rubio , Balaram Sinharoy
发明人： Ravi K. Arimilli , Juan C. Rubio , Balaram Sinharoy
IPC分类号： G06F9/30
CPC分类号： G06F9/4843 , G06F9/3851
摘要： A set of helper thread binaries is created to retrieve data used by a set of main thread binaries. The set of helper thread binaries and the set of main thread binaries are partitioned according to common instruction boundaries. As a first partition in the set of main thread binaries executes within a first core, a second partition in the set of helper thread binaries executes within a second core, thus “warming up” the cache in the second core. When the first partition of the main completes execution, a second partition of the main core moves to the second core, and executes using the warmed up cache in the second core.
摘要翻译：创建一组辅助线程二进制文件来检索一组主线程二进制文件使用的数据。辅助线程二进制文件集和主线程二进制文件集合根据公共指令边界进行分区。作为主线程二进制文件集合中的第一分区在第一核心内执行，该辅助线程二进制文件集中的第二分区在第二核心内执行，从而“预热”第二核心中的高速缓存。当主要的第一分区完成执行时，主核心的第二分区移动到第二核心，并使用第二核心中的预热高速缓存执行。

8. 发明授权

US08387065B2 Speculative popcount data creation 有权
标题翻译：投机性的popcount数据创建
公开(公告)号：US08387065B2
公开(公告)日：2013-02-26
申请号：US12425343
申请日：2009-04-16
申请人： Ravi K. Arimilli , Ronald N. Kalla , Balaram Sinharoy
发明人： Ravi K. Arimilli , Ronald N. Kalla , Balaram Sinharoy
IPC分类号： G06F9/46 , G06F9/45 , G06F9/30 , G06F9/40
CPC分类号： G06F9/3001 , G06F9/30018 , G06F9/3842
摘要： A method and a data processing system by which population count (popcount) operations are efficiently performed without incurring the latency and loss of critical processing cycles and bandwidth of real time processing. The method comprises: identifying data to be stored to memory for which a popcount may need to be determined; speculatively performing a popcount operation on the data as a background process of the processor while the data is being stored to memory; storing the data to a first memory location; and storing a value of the popcount generated by the popcount operation within a second memory location. The method further comprises: determining a size of data; determining a granular level at which the popcount operation on the data will be performed; and reserving a size of said second memory location that is sufficiently large to hold the value of the popcount.
摘要翻译：一种方法和数据处理系统，通过该方法和数据处理系统有效地执行人口计数（popcount）操作，而不会导致关键处理周期的延迟和丢失以及实时处理的带宽。该方法包括：识别要存储到可能需要确定一个弹出窗口的存储器的数据; 在将数据存储到存储器中的情况下，作为处理器的后台处理推测性地对数据进行弹出数据操作; 将数据存储到第一存储器位置; 以及将由所述popcount操作生成的所述popcount的值存储在第二存储器位置内。该方法还包括：确定数据的大小; 确定将执行对数据的弹出数据操作的粒度级别; 以及保留所述第二存储器位置的大小足够大以保持所述用户名的值。

9. 发明授权

US08359589B2 Helper thread for pre-fetching data 失效
标题翻译：辅助线程用于预取数据
公开(公告)号：US08359589B2
公开(公告)日：2013-01-22
申请号：US12024191
申请日：2008-02-01
申请人： Ravi K. Arimilli , Juan C. Rubio , Balaram Sinharoy
发明人： Ravi K. Arimilli , Juan C. Rubio , Balaram Sinharoy
IPC分类号： G06F9/44 , G06F9/45 , G06F15/167 , G06F9/30 , G06F9/46
CPC分类号： G06F8/41 , G06F9/383 , G06F9/3851
摘要： A set of helper thread binaries is created to retrieve data used by a set of main thread binaries. If executing a portion of the set of helper thread binaries results in the retrieval of data needed by the set of main thread binaries, then that retrieved data is utilized by the set of main thread binaries.
摘要翻译：创建一组辅助线程二进制文件来检索一组主线程二进制文件使用的数据。如果执行一组辅助线程二进制文件的一部分导致检索主线程二进制文件集所需的数据，那么该检索的数据由主线程二进制文件集合使用。

10. 发明授权

US08285971B2 Block driven computation with an address generation accelerator 失效
标题翻译：使用地址生成加速器进行块驱动计算
公开(公告)号：US08285971B2
公开(公告)日：2012-10-09
申请号：US12336315
申请日：2008-12-16
申请人： Ravi K. Arimilli , Balaram Sinharoy
发明人： Ravi K. Arimilli , Balaram Sinharoy
IPC分类号： G06F12/00
CPC分类号： G06F9/383 , G06F9/30094 , G06F9/345
摘要： A processor includes at least one execution unit that executes instructions, at least one register file, coupled to the at least one execution unit, that buffers operands for access by the at least one execution unit, an instruction sequencing unit that fetches instructions for execution by the at least one execution unit, and an address generation accelerator. The address generation accelerator, responsive to an initiation signal received from the instruction sequencing unit, computes and outputs first and second effective addresses of operands of an operation.
摘要翻译：处理器包括执行指令的至少一个执行单元，耦合到所述至少一个执行单元的至少一个寄存器文件，其缓冲由所述至少一个执行单元访问的操作数，指令排序单元，其通过所述至少一个执行单元和地址生成加速器。地址产生加速器响应于从指令排序单元接收的发起信号，计算并输出操作的操作数的第一和第二有效地址。

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