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1. 发明授权

US07716506B1 Apparatus, method, and system for dynamically selecting power down level 有权
标题翻译：用于动态选择掉电电平的装置，方法和系统
公开(公告)号：US07716506B1
公开(公告)日：2010-05-11
申请号：US11611118
申请日：2006-12-14
申请人： Roman Surgutchik , Robert William Chapman , Edward L. Riegelsberger , Brad W. Simeral , Paul J. Gyugyi
发明人： Roman Surgutchik , Robert William Chapman , Edward L. Riegelsberger , Brad W. Simeral , Paul J. Gyugyi
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/3287 , Y02D10/171
摘要： A system has a plurality of different clients. Each client generates a report signal indicative of a current latency tolerance associated with a performance state. A controller dynamically determines a power down level having a minimum power consumption capable of supporting the system latency of the configuration state of the clients.
摘要翻译：系统具有多个不同的客户端。每个客户端生成指示与性能状态相关联的当前延迟容限的报告信号。控制器动态地确定具有能够支持客户端的配置状态的系统延迟的最小功耗的掉电电平。

2. 发明申请

US20100008176A1 Write Leveling Of Memory Units Designed To Receive Access Requests In A Sequential Chained Topology 有权
标题翻译：写入顺序链接拓扑中接收访问请求的内存单元的调平
公开(公告)号：US20100008176A1
公开(公告)日：2010-01-14
申请号：US12169662
申请日：2008-07-09
申请人： Jyotirmaya Swain , Edward L. Riegelsberger , Utpal Barman
发明人： Jyotirmaya Swain , Edward L. Riegelsberger , Utpal Barman
IPC分类号： G11C8/18 , G11C8/00
CPC分类号： G11C8/18 , G11C7/10 , G11C7/1072 , G11C7/1078 , G11C7/1093 , G11C11/4076
摘要： A memory controller provided according to an aspect of the present invention uses a slower clock signal during write leveling compared to when performing write operations thereafter. Due to such use of a slower clock signal, the various desired delays can be determined accurately and/or easily. In an embodiment, the frequency of the slower clock signal is determined based on the maximum fly-by delay (generally the delay between sending of a signal on the shared sequential path and the receipt at the memory unit in the sequence) that may be present in the memory system. For example, if the fly by delay can be M (an integer) times the time period of the clock signal during normal write operations, the slower clock signal may have a time period of M times that of the clock signal during write operation.
摘要翻译：根据本发明的一个方面提供的存储器控制器在与写入操作之间执行写入操作时相比，在写入调平期间使用较慢的时钟信号。由于这种使用较慢的时钟信号，可以精确地和/或容易地确定各种期望的延迟。在一个实施例中，较慢时钟信号的频率基于可能存在的最大飞越延迟（通常是在共享顺序路径上发送信号和在序列中的存储器单元处的接收之间的延迟）来确定在内存系统中。例如，如果在正常写入操作期间延迟的飞行可以是时钟信号的时间的M（整数）倍，则较慢的时钟信号可以具有在写入操作期间的时钟周期的M倍的时间周期。

3. 发明授权

US07342590B1 Screen compression 有权
标题翻译：屏幕压缩
公开(公告)号：US07342590B1
公开(公告)日：2008-03-11
申请号：US10435073
申请日：2003-05-09
申请人： John M. Danskin , Ziyad S. Hakura , Edward L. Riegelsberger , Jason M. Musicer , Stephen D. Lew
发明人： John M. Danskin , Ziyad S. Hakura , Edward L. Riegelsberger , Jason M. Musicer , Stephen D. Lew
IPC分类号： G06T9/00 , G06K9/36
CPC分类号： G09G5/397 , G09G5/393 , G09G2340/02 , G09G2340/12 , G09G2360/122 , H04N19/428 , H04N19/593
摘要： Methods, circuits, and apparatus for reducing memory bandwidth used by a graphics processor. Uncompressed tiles are read from a display buffer portion of a graphics memory and received by an encoder. The uncompressed tiles are compressed and written back to the graphics memory. When a tile is needed again before it has been modified, the compressed version is read from memory, uncompressed, and displayed. To reduce the number of unnecessary writes of compressed tiles to memory, a tile is only written to memory if it has remained static for some number of refresh cycles. Also, to prevent a large number of compressed tiles being written to the display buffer in one refresh cycle, the encoder can be throttled after a number of tiles have been written. Validity information can be stored for use by a CRTC. If a tile is updated, the validity information is updated such that invalid compressed data is not read from memory and displayed.
摘要翻译：用于减少由图形处理器使用的存储器带宽的方法，电路和装置。未压缩的瓦片从图形存储器的显示缓冲器部分读取并由编码器接收。未压缩的瓦片被压缩并写回图形存储器。在修改瓦片之前，再次需要一个瓦片时，从内存中读取压缩版本，解压缩并显示。为了将压缩瓦片的不必要的写入数量减少到存储器，如果在一些刷新周期内保持静态，则瓦片仅写入存储器。此外，为了防止在一个刷新周期中将大量的压缩瓦片写入显示缓冲器，编码器可以在写入多个瓦片之后被节流。有效信息可以存储供CRTC使用。如果更新瓦片，则更新有效性信息，使得无法从存储器读取无效的压缩数据并显示。

4. 发明申请

US20140032947A1 TRAINING, POWER-GATING, AND DYNAMIC FREQUENCY CHANGING OF A MEMORY CONTROLLER 有权
标题翻译：记忆控制器的训练，功率增益和动态频率变化
公开(公告)号：US20140032947A1
公开(公告)日：2014-01-30
申请号：US13561884
申请日：2012-07-30
申请人： Sagheer Ahmad , Edward L. Riegelsberger , Tony Yuhsiang Cheng , Laurent Rene Moll , Brian Keith Langendorf
发明人： Sagheer Ahmad , Edward L. Riegelsberger , Tony Yuhsiang Cheng , Laurent Rene Moll , Brian Keith Langendorf
IPC分类号： G06F1/00
CPC分类号： G06F1/3275 , G06F9/4418 , Y02D10/14 , Y02D50/20
摘要： A method for managing a memory controller comprising selecting a low-power state from a plurality of low-power states. The method further comprises transitioning to the low-power and entering the low-power state when the transition is complete, provided a wake-event has not been received. An apparatus comprises a controller configured to select a power state for transition, a state-machine configured to execute steps for transitions between power states of a memory controller connected by a bus to a memory, a storage configured to store at least one context, and a context engine configured to stream, at the direction of the state-machine engine, the at least one context to the memory controller. Streaming comprises communicating N portions of context data as a stream to N registers in the memory controller. A context comprises a plurality of calibrations corresponding to a state selected for transition.
摘要翻译：一种用于管理存储器控制器的方法，包括从多个低功率状态中选择低功率状态。该方法还包括：当转换完成时，转换到低功率并进入低功率状态，只要没有接收到唤醒事件。一种装置包括：控制器，被配置为选择用于转换的功率状态;状态机，被配置为执行用于通过总线连接到存储器的存储器控制器的功率状态之间的转换的步骤;被配置为存储至少一个上下文的存储器;以及上下文引擎，被配置为在所述状态机引擎的方向上将所述至少一个上下文流向所述存储器控制器。流式传输包括将上下文数据的N个部分作为流传送到存储器控制器中的N个寄存器。上下文包括对应于选择用于转换的状态的多个校准。

5. 发明授权

US07965895B1 Screen compression 有权
标题翻译：屏幕压缩
公开(公告)号：US07965895B1
公开(公告)日：2011-06-21
申请号：US11837336
申请日：2007-08-10
申请人： John M. Danskin , Ziyad S. Hakura , Edward L. Riegelsberger , Jason M. Musicer , Stephen D. Lew
发明人： John M. Danskin , Ziyad S. Hakura , Edward L. Riegelsberger , Jason M. Musicer , Stephen D. Lew
IPC分类号： G06K9/36 , G06K9/46
CPC分类号： G09G5/397 , G09G5/393 , G09G2340/02 , G09G2340/12 , G09G2360/122 , H04N19/428 , H04N19/593
摘要： Methods, circuits, and apparatus for reducing memory bandwidth used by a graphics processor. Uncompressed tiles are read from a display buffer portion of a graphics memory and received by an encoder. The uncompressed tiles are compressed and written back to the graphics memory. When a tile is needed again before it has been modified, the compressed version is read from memory, uncompressed, and displayed. To reduce the number of unnecessary writes of compressed tiles to memory, a tile is only written to memory if it has remained static for some number of refresh cycles. Also, to prevent a large number of compressed tiles being written to the display buffer in one refresh cycle, the encoder can be throttled after a number of tiles have been written. Validity information can be stored for use by a CRTC. If a tile is updated, the validity information is updated such that invalid compressed data is not read from memory and displayed.
摘要翻译：用于减少由图形处理器使用的存储器带宽的方法，电路和装置。未压缩的瓦片从图形存储器的显示缓冲器部分读取并由编码器接收。未压缩的瓦片被压缩并写回图形存储器。在修改瓦片之前，再次需要一个瓦片时，从内存中读取压缩版本，解压缩并显示。为了将压缩瓦片的不必要的写入数量减少到存储器，如果在一些刷新周期内保持静态，则瓦片仅写入存储器。此外，为了防止在一个刷新周期中将大量的压缩瓦片写入显示缓冲器，编码器可以在写入多个瓦片之后被节流。有效信息可以存储供CRTC使用。如果更新瓦片，则更新有效性信息，使得无法从存储器读取无效的压缩数据并显示。

6. 发明申请

US20100008158A1 Read Leveling Of Memory Units Designed To Receive Access Requests In A Sequential Chained Topology 有权
标题翻译：读取设计用于在连续链接拓扑中接收访问请求的内存单元的调整
公开(公告)号：US20100008158A1
公开(公告)日：2010-01-14
申请号：US12168948
申请日：2008-07-08
申请人： Jyotirmaya Swain , Edward L. Riegelsberger , Utpal Barman
发明人： Jyotirmaya Swain , Edward L. Riegelsberger , Utpal Barman
IPC分类号： G11C7/00
CPC分类号： G11C29/02 , G11C5/04 , G11C7/1066 , G11C11/401 , G11C29/022 , G11C29/023 , G11C29/028 , G11C2207/2254
摘要： Read leveling of memory units designed to receive access requests in a sequential chained topology writing a data pattern to the memory array. In an embodiment, a memory controller first writes a desired pattern into the memory array of a memory unit and then iteratively determines the accurate calibrated delay by setting a compensation delay to a test value, reading a data portion from the memory array based on the test value for the compensation delay, comparing the data portion with an expected data, determining that the test value is a calibrated compensation delay for the memory unit if the data portion equals the expected value.
摘要翻译：读取设计用于在将数据模式写入存储器阵列的连续链接拓扑中接收访问请求的存储器单元的调平。在一个实施例中，存储器控制器首先将期望的图案写入存储器单元的存储器阵列中，然后通过将补偿延迟设置为测试值来迭代地确定精确的校准延迟，基于测试从存储器阵列读取数据部分用于补偿延迟的值，将数据部分与预期数据进行比较，如果数据部分等于期望值，则确定测试值是存储器单元的校准补偿延迟。

7. 发明授权

US09104421B2 Training, power-gating, and dynamic frequency changing of a memory controller 有权
标题翻译：内存控制器的训练，电源选通和动态变频
公开(公告)号：US09104421B2
公开(公告)日：2015-08-11
申请号：US13561884
申请日：2012-07-30
申请人： Sagheer Ahmad , Edward L. Riegelsberger , Tony Yuhsiang Cheng , Laurent Rene Moll , Brian Keith Langendorf
发明人： Sagheer Ahmad , Edward L. Riegelsberger , Tony Yuhsiang Cheng , Laurent Rene Moll , Brian Keith Langendorf
IPC分类号： G06F1/32 , G06F9/44
CPC分类号： G06F1/3275 , G06F9/4418 , Y02D10/14 , Y02D50/20
摘要： A method for managing a memory controller comprising selecting a low-power state from a plurality of low-power states. The method further comprises transitioning to the low-power and entering the low-power state when the transition is complete, provided a wake-event has not been received. An apparatus comprises a controller configured to select a power state for transition, a state-machine configured to execute steps for transitions between power states of a memory controller connected by a bus to a memory, a storage configured to store at least one context, and a context engine configured to stream, at the direction of the state-machine engine, the at least one context to the memory controller. Streaming comprises communicating N portions of context data as a stream to N registers in the memory controller. A context comprises a plurality of calibrations corresponding to a state selected for transition.
摘要翻译：一种用于管理存储器控制器的方法，包括从多个低功率状态中选择低功率状态。该方法还包括：当转换完成时，转换到低功率并进入低功率状态，只要没有接收到唤醒事件。一种装置包括：控制器，被配置为选择用于转换的功率状态;状态机，被配置为执行用于通过总线连接到存储器的存储器控制器的功率状态之间的转换的步骤;被配置为存储至少一个上下文的存储器;以及上下文引擎，被配置为在所述状态机引擎的方向上将所述至少一个上下文流向所述存储器控制器。流式传输包括将上下文数据的N个部分作为流传送到存储器控制器中的N个寄存器。上下文包括对应于选择用于转换的状态的多个校准。

8. 发明授权

US08768494B1 System and method for generating policy-based audio 有权
标题翻译：用于生成基于策略的音频的系统和方法
公开(公告)号：US08768494B1
公开(公告)日：2014-07-01
申请号：US10744678
申请日：2003-12-22
申请人： Micah S. Stroud , Stephen G. Holmes , Edward L. Riegelsberger
发明人： Micah S. Stroud , Stephen G. Holmes , Edward L. Riegelsberger
IPC分类号： G06F17/00
CPC分类号： H04S7/30 , G06F3/165 , G08B13/19682 , H04S2400/11 , H04S2400/13
摘要： Embodiments of the invention provide a policy-based audio system. The system includes a sound application protocol interface, a configuration module and a speaker driver. The sound application protocol interface receives a set of sound samples generated by an application or event. The configuration module retrieves a first group of one or more parameters, rules and priorities applicable to the application or event. The speaker driver produces an audio output by processing the set of sound samples as a function of the group of one or more configuration parameters, rules and priorities.
摘要翻译：本发明的实施例提供了一种基于策略的音频系统。该系统包括声音应用协议接口，配置模块和扬声器驱动器。声音应用协议接口接收由应用或事件生成的一组声音样本。配置模块检索适用于应用程序或事件的第一组一个或多个参数，规则和优先级。扬声器驱动器通过根据一个或多个配置参数，规则和优先级的组来处理该组声音样本来产生音频输出。

9. 发明申请

US20100039149A1 Programmable Delay Circuit Providing For A Wide Span Of Delays 有权
标题翻译：可编程延迟电路提供广泛的延迟
公开(公告)号：US20100039149A1
公开(公告)日：2010-02-18
申请号：US12189823
申请日：2008-08-12
申请人： Jyotirmaya Swain , Utpal Barman , Adarsh Kalliat , Raji Cherian , Edward L. Riegelsberger
发明人： Jyotirmaya Swain , Utpal Barman , Adarsh Kalliat , Raji Cherian , Edward L. Riegelsberger
IPC分类号： H03L7/00
CPC分类号： H04L7/00 , H04L7/0045
摘要： According to an aspect of the present invention, one of multiple clock signals of different relative phases is selected based on a desired delay magnitude, and the digital values received on an input signal are then synchronized to an edge (“first edge”) of the selected clock signal to provide the digital values with the desired delay magnitude. In an embodiment, the selected clock signal can be delayed by a fine value (less than the minimum phase difference of the multiple clock signals) to provide a wide span of desired delays. An aspect of the invention provides for a synchronization circuit with reduced latency and which is substantially invariant to process, voltage and temperature (PVT) changes.
摘要翻译：根据本发明的一个方面，基于期望的延迟幅度选择不同相对相位的多个时钟信号之一，并且在输入信号上接收的数字值然后被同步到所述延迟幅度的边缘（“第一边缘”）所选择的时钟信号以期望的延迟幅度提供数字值。在一个实施例中，所选择的时钟信号可以被延迟一个精细值（小于多个时钟信号的最小相位差），以提供大范围的期望延迟。本发明的一个方面提供了具有降低的等待时间并且对于处理，电压和温度（PVT）变化基本上不变的同步电路。

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