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1. 发明授权

US07962725B2 Pre-decoding variable length instructions 有权
标题翻译：预解码可变长度指令
公开(公告)号：US07962725B2
公开(公告)日：2011-06-14
申请号：US11381545
申请日：2006-05-04
申请人： Rodney Wayne Smith , Brian Michael Stempel
发明人： Rodney Wayne Smith , Brian Michael Stempel
IPC分类号： G06F9/30 , G06F9/40 , G06F7/38 , G06F9/00 , G06F9/44
CPC分类号： G06F9/30149 , G06F9/30152 , G06F9/30185 , G06F9/30192 , G06F9/3802 , G06F9/382
摘要： A pre-decoder in a variable instruction length processor indicates properties of instructions in pre-decode bits stored in an instruction cache with the instructions. When all the encodings of pre-decode bits associate with one length instruction are defined, a property of an instruction of that length may be indicated by altering the instruction to emulate an instruction of a different length, and encoding the property in the pre-decode bits associated with instructions of the different length. One example of a property that may be so indicated is an undefined instruction.
摘要翻译：可变指令长度处理器中的预解码器指示存储在具有指令的指令高速缓存中的预解码位中的指令的特性。当预解码位的所有编码与一个长度指令相关联时，可以通过改变指令来模拟不同长度的指令来指示该长度的指令的属性，并且在预解码中编码该属性与不同长度的指令相关联的位。可能如此指示的属性的一个示例是未定义的指令。

2. 发明授权

US07917731B2 Method and apparatus for prefetching non-sequential instruction addresses 有权
标题翻译：用于预取非顺序指令地址的方法和装置
公开(公告)号：US07917731B2
公开(公告)日：2011-03-29
申请号：US11461883
申请日：2006-08-02
申请人： Brian Michael Stempel , Thomas Andrew Sartorius , Rodney Wayne Smith
发明人： Brian Michael Stempel , Thomas Andrew Sartorius , Rodney Wayne Smith
IPC分类号： G06F9/32
CPC分类号： G06F9/3804 , G06F9/3806
摘要： A processor performs a prefetch operation on non-sequential instruction addresses. If a first instruction address misses in an instruction cache and accesses a higher-order memory as part of a fetch operation, and a branch instruction associated with the first instruction address or an address following the first instruction address is detected and predicted taken, a prefetch operation is performed using a predicted branch target address, during the higher-order memory access. If the predicted branch target address hits in the instruction cache during the prefetch operation, associated instructions are not retrieved, to conserve power. If the predicted branch target address misses in the instruction cache during the prefetch operation, a higher-order memory access may be launched, using the predicted branch instruction address. In either case, the first instruction address is re-loaded into the fetch stage pipeline to await the return of instructions from its higher-order memory access.
摘要翻译：处理器对非顺序指令地址执行预取操作。如果第一指令地址在指令高速缓存中丢失并且作为获取操作的一部分访问高阶存储器，并且检测并预测与第一指令地址或第一指令地址之后的地址相关联的分支指令，则预取在高级存储器访问期间使用预测的分支目标地址执行操作。如果预取分支目标地址在预取操作期间在指令高速缓存中命中，则不检索相关联的指令以节省功率。如果在预取操作期间预测的分支目标地址在指令高速缓存中丢失，则可以使用预测的分支指令地址来启动高阶存储器访问。在任一种情况下，第一指令地址被重新加载到提取级流水线中以等待指令从其高阶存储器访问返回。

3. 发明申请

US20080229069A1 System, Method And Software To Preload Instructions From An Instruction Set Other Than One Currently Executing 有权
标题翻译：系统，方法和软件可以从目前正在执行的指令集预加载指令
公开(公告)号：US20080229069A1
公开(公告)日：2008-09-18
申请号：US11685850
申请日：2007-03-14
申请人： Thomas Andrew Sartorius , Brian Michael Stempel , Rodney Wayne Smith
发明人： Thomas Andrew Sartorius , Brian Michael Stempel , Rodney Wayne Smith
IPC分类号： G06F9/44 , G06F9/30
CPC分类号： G06F9/30196 , G06F9/30047 , G06F9/30189 , G06F9/3802 , G06F9/382
摘要： An instruction preload instruction executed in a first processor instruction set operating mode is operative to correctly preload instructions in a different, second instruction set. The instructions are pre-decoded according to the second instruction set encoding in response to an instruction set preload indicator (ISPI). In various embodiments, the ISPI may be set prior to executing the preload instruction, or may comprise part of the preload instruction or the preload target address.
摘要翻译：在第一处理器指令集操作模式中执行的指令预加载指令可操作以在不同的第二指令集中正确地预加载指令。根据指令集预加载指示符（ISPI），根据第二指令集编码对指令进行预解码。在各种实施例中，可以在执行预加载指令之前设置ISPI，或者可以包括预加载指令或预加载目标地址的一部分。

4. 发明授权

US07406613B2 Translation lookaside buffer (TLB) suppression for intra-page program counter relative or absolute address branch instructions 有权
标题翻译：翻译后备缓冲器（TLB）抑制用于页内程序计数器相对或绝对地址分支指令
公开(公告)号：US07406613B2
公开(公告)日：2008-07-29
申请号：US11003772
申请日：2004-12-02
申请人： James Norris Dieffenderfer , Thomas Andrew Sartorius , Rodney Wayne Smith , Brian Michael Stempel
发明人： James Norris Dieffenderfer , Thomas Andrew Sartorius , Rodney Wayne Smith , Brian Michael Stempel
IPC分类号： G06F1/26
CPC分类号： G06F12/1027 , G06F9/30054 , G06F9/32 , G06F9/3804 , G06F9/382 , G06F2212/1028 , G06F2212/655 , Y02D10/13
摘要： In a pipelined processor, a pre-decoder in advance of an instruction cache calculates the branch target address (BTA) of PC-relative and absolute address branch instructions. The pre-decoder compares the BTA with the branch instruction address (BIA) to determine whether the target and instruction are in the same memory page. A branch target same page (BTSP) bit indicating this is written to the cache and associated with the instruction. When the branch is executed and evaluated as taken, a TLB access to check permission attributes for the BTA is suppressed if the BTA is in the same page as the BIA, as indicated by the BTSP bit. This reduces power consumption as the TLB access is suppressed and the BTA/BIA comparison is only performed once, when the branch instruction is first fetched. Additionally, the pre-decoder removes the BTA/BIA comparison from the BTA generation and selection critical path.
摘要翻译：在流水线处理器中，在指令高速缓存之前的预解码器计算PC相对的分支目标地址（BTA）和绝对地址分支指令。预解码器将BTA与分支指令地址（BIA）进行比较，以确定目标和指令是否在相同的存储器页面中。指示这一点的分支目标相同页（BTSP）位被写入高速缓存并与指令相关联。当分支被执行并被评估时，如果BTA与BIA在同一个页面中，如BTSP位所指示的那样，则抑制对BTA的许可属性的TLB访问被抑制。当首先取出分支指令时，这样可以降低TLB访问的功耗，并且仅执行一次BTA / BIA比较。另外，预解码器从BTA生成和选择关键路径去除BTA / BIA比较。

5. 发明授权

US08438372B2 Link stack repair of erroneous speculative update 失效
标题翻译：链接堆栈修复错误的推测更新
公开(公告)号：US08438372B2
公开(公告)日：2013-05-07
申请号：US13212654
申请日：2011-08-18
申请人： James Norris Dieffenderfer , Brian Michael Stempel , Rodney Wayne Smith
发明人： James Norris Dieffenderfer , Brian Michael Stempel , Rodney Wayne Smith
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/30054 , G06F9/3806 , G06F9/3863
摘要： Whenever a link address is written to the link stack, the prior value of the link stack entry is saved, and is restored to the link stack after a link stack push operation is speculatively executed following a mispredicted branch. This condition is detected by maintaining an incrementing tag register which is incremented by each link stack write instruction entering the pipeline, and a snapshot of the incrementing tag register, associated with each branch instruction. When a branch is evaluated and determined to have been mispredicted, the snapshot associated with it is compared to the incrementing tag register. A discrepancy indicates a link stack write instruction was speculatively issued into the pipeline after the mispredicted branch instruction, and pushed a link address onto the link stack, thus corrupting the link stack. The prior link address is restored to the link stack from the link stack restore buffer.
摘要翻译：每当链接地址被写入链接堆栈时，链接堆栈条目的先前值被保存，并且在错误预测的分支之后推测地执行链路堆叠推送操作之后被还原到链路栈。通过保持由进入管线的每个链路堆栈写入指令递增的递增标签寄存器以及与每个分支指令相关联的递增标签寄存器的快照来检测该条件。当分支被评估并被确定为被错误预测时，将与之相关联的快照与增量标签寄存器进行比较。一个差异表示在错误预测的分支指令之后推测发布了一个链路堆栈写入指令，并将链路地址推送到链路堆栈上，从而破坏了链路堆栈。链路堆栈恢复缓冲区中的链路栈恢复到先前的链路地址。

6. 发明申请

US20110320790A1 Link Stack Repair of Erroneous Speculative Update 失效
标题翻译：链接堆栈修复错误的投机更新
公开(公告)号：US20110320790A1
公开(公告)日：2011-12-29
申请号：US13212654
申请日：2011-08-18
申请人： James Norris Dieffenderfer , Brian Michael Stempel , Rodney Wayne Smith
发明人： James Norris Dieffenderfer , Brian Michael Stempel , Rodney Wayne Smith
IPC分类号： G06F9/38
CPC分类号： G06F9/3842 , G06F9/30054 , G06F9/3806 , G06F9/3863
摘要： Whenever a link address is written to the link stack, the prior value of the link stack entry is saved, and is restored to the link stack after a link stack push operation is speculatively executed following a mispredicted branch. This condition is detected by maintaining an incrementing tag register which is incremented by each link stack write instruction entering the pipeline, and a snapshot of the incrementing tag register, associated with each branch instruction. When a branch is evaluated and determined to have been mispredicted, the snapshot associated with it is compared to the incrementing tag register. A discrepancy indicates a link stack write instruction was speculatively issued into the pipeline after the mispredicted branch instruction, and pushed a link address onto the link stack, thus corrupting the link stack. The prior link address is restored to the link stack from the link stack restore buffer.
摘要翻译：每当链接地址被写入链接堆栈时，链接堆栈条目的先前值被保存，并且在错误预测的分支之后推测地执行链路堆叠推送操作之后被还原到链路栈。通过保持由进入管线的每个链路堆栈写入指令递增的递增标签寄存器以及与每个分支指令相关联的递增标签寄存器的快照来检测该条件。当分支被评估并被确定为被错误预测时，将与之相关联的快照与增量标签寄存器进行比较。一个差异表示在错误预测的分支指令之后推测发布了一个链路堆栈写入指令，并将链路地址推送到链路堆栈上，从而破坏了链路堆栈。链路堆栈恢复缓冲区中的链路栈恢复到先前的链路地址。

7. 发明申请

US20110219220A1 Link Stack Repair of Erroneous Speculative Update 有权
标题翻译：链接堆栈修复错误的投机更新
公开(公告)号：US20110219220A1
公开(公告)日：2011-09-08
申请号：US13108227
申请日：2011-05-16
申请人： James Norris Dieffenderfer , Brian Michael Stempel , Rodney Wayne Smith
发明人： James Norris Dieffenderfer , Brian Michael Stempel , Rodney Wayne Smith
IPC分类号： G06F9/38
CPC分类号： G06F9/3842 , G06F9/3806 , G06F9/3861
摘要： Whenever a link address is written to the link stack, the prior value of the link stack entry is saved, and is restored to the link stack after a link stack push operation is speculatively executed following a mispredicted branch. This condition is detected by maintaining a count of the total number of uncommitted link stack write instructions in the pipeline, and a count of the number of uncommitted link stack write instructions ahead of each branch instruction. When a branch is evaluated and determined to have been mispredicted, the count associated with it is compared to the total count. A discrepancy indicates a link stack write instruction was speculatively issued into the pipeline after the mispredicted branch instruction, and pushed a link address onto the link stack. The prior link address is restored to the link stack from the link stack restore buffer.
摘要翻译：每当链接地址被写入链接堆栈时，链接堆栈条目的先前值被保存，并且在错误预测的分支之后推测地执行链路堆叠推送操作之后被还原到链路栈。通过维持流水线中未提交的链路堆栈写入指令的总数的计数以及每个分支指令之前的未提交的链路栈写入指令的数量的计数来检测该条件。当分支被评估并确定为被误判时，将与之相关联的计数与总计数进行比较。一个差异表示在错误预测的分支指令之后推测发布了一个链接堆栈写入指令，并将链路地址推送到链路堆栈上。链路堆栈恢复缓冲区中的链路栈恢复到先前的链路地址。

8. 发明授权

US07650466B2 Method and apparatus for managing cache partitioning using a dynamic boundary 有权
标题翻译：使用动态边界管理缓存分区的方法和装置
公开(公告)号：US07650466B2
公开(公告)日：2010-01-19
申请号：US11233575
申请日：2005-09-21
申请人： Brian Michael Stempel , James Norris Dieffenderfer , Jeffrey Todd Bridges , Thomas Andrew Sartorius , Rodney Wayne Smith , Robert Douglas Clancy , Victor Roberts Augsburg
发明人： Brian Michael Stempel , James Norris Dieffenderfer , Jeffrey Todd Bridges , Thomas Andrew Sartorius , Rodney Wayne Smith , Robert Douglas Clancy , Victor Roberts Augsburg
IPC分类号： G06F12/00
CPC分类号： G06F12/126
摘要： A method of managing cache partitions provides a first pointer for higher priority writes and a second pointer for lower priority writes, and uses the first pointer to delimit the lower priority writes. For example, locked writes have greater priority than unlocked writes, and a first pointer may be used for locked writes, and a second pointer may be used for unlocked writes. The first pointer is advanced responsive to making locked writes, and its advancement thus defines a locked region and an unlocked region. The second pointer is advanced responsive to making unlocked writes. The second pointer also is advanced (or retreated) as needed to prevent it from pointing to locations already traversed by the first pointer. Thus, the pointer delimits the unlocked region and allows the locked region to grow at the expense of the unlocked region.
摘要翻译：管理高速缓存分区的方法提供用于较高优先级写入的第一指针和用于较低优先级写入的第二指针，并且使用第一指针来划分较低优先级的写入。例如，锁定的写入具有比解锁的写入更高的优先级，并且第一指针可以用于锁定的写入，并且第二指针可以用于解锁的写入。响应于锁定写入，第一指针是高级的，并且其进步因此定义了锁定区域和解锁区域。响应于解锁写入，第二个指针是高级的。第二个指针也根据需要进行高级（或撤销），以防止它指向已经被第一个指针所遍历的位置。因此，指针限定未锁定区域，并允许锁定区域以解锁区域为代价而增长。

9. 发明授权

US07617387B2 Methods and system for resolving simultaneous predicted branch instructions 有权
标题翻译：解决同步预测分支指令的方法和系统
公开(公告)号：US07617387B2
公开(公告)日：2009-11-10
申请号：US11535536
申请日：2006-09-27
申请人： Rodney Wayne Smith , Brian Michael Stempel , James Norris Dieffenderfer , Thomas Andrew Sartorius
发明人： Rodney Wayne Smith , Brian Michael Stempel , James Norris Dieffenderfer , Thomas Andrew Sartorius
IPC分类号： G06F9/00 , G06F9/30
CPC分类号： G06F9/3885 , G06F9/30058 , G06F9/3844 , G06F9/3861
摘要： A method of resolving simultaneous branch predictions prior to validation of the predicted branch instruction is disclosed. The method includes processing two or more predicted branch instructions, with each predicted branch instruction having a predicted state and a corrected state. The method further includes selecting one of the corrected states. Should one of the predicted branch instructions be mispredicted, the selected corrected state is used to direct future instruction fetches.
摘要翻译：公开了一种在预测分支指令验证之前解决同步分支预测的方法。该方法包括处理两个或多个预测分支指令，每个预测分支指令具有预测状态和校正状态。该方法还包括选择一个校正状态。如果预测的分支指令之一被错误预测，则所选择的校正状态用于指示未来的指令提取。

10. 发明申请

US20090094444A1 Link Stack Repair of Erroneous Speculative Update 有权
标题翻译：链接堆栈修复错误的投机更新
公开(公告)号：US20090094444A1
公开(公告)日：2009-04-09
申请号：US11867727
申请日：2007-10-05
申请人： James Norris Dieffenderfer , Brian Michael Stempel , Rodney Wayne Smith
发明人： James Norris Dieffenderfer , Brian Michael Stempel , Rodney Wayne Smith
IPC分类号： G06F9/312
CPC分类号： G06F9/3842 , G06F9/3806 , G06F9/3861
摘要： Whenever a link address is written to the link stack, the prior value of the link stack entry is saved, and is restored to the link stack after a link stack push operation is speculatively executed following a mispredicted branch. This condition is detected by maintaining a count of the total number of uncommitted link stack write instructions in the pipeline, and a count of the number of uncommitted link stack write instructions ahead of each branch instruction. When a branch is evaluated and determined to have been mispredicted, the count associated with it is compared to the total count. A discrepancy indicates a link stack write instruction was speculatively issued into the pipeline after the mispredicted branch instruction, and pushed a link address onto the link stack. The prior link address is restored to the link stack from the link stack restore buffer.
摘要翻译：每当链接地址被写入链接堆栈时，链接堆栈条目的先前值被保存，并且在错误预测的分支之后推测地执行链路堆叠推送操作之后被还原到链路栈。通过维持流水线中未提交的链路堆栈写入指令的总数的计数以及每个分支指令之前的未提交的链路栈写入指令的数量的计数来检测该条件。当分支被评估并确定为被误判时，将与之相关联的计数与总计数进行比较。一个差异表示在错误预测的分支指令之后推测发布了一个链接堆栈写入指令，并将链路地址推送到链路堆栈上。链路堆栈恢复缓冲区中的链路栈恢复到先前的链路地址。

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