专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20090242385A1 METHOD OF DEPOSITING METAL-CONTAINING FILMS BY INDUCTIVELY COUPLED PHYSICAL VAPOR DEPOSITION 审中-公开
标题翻译：通过电感耦合物理蒸发沉积沉积含金属膜的方法
公开(公告)号：US20090242385A1
公开(公告)日：2009-10-01
申请号：US12058607
申请日：2008-03-28
申请人： Rodney L. Robison , Frank M. Cerio, JR.
发明人： Rodney L. Robison , Frank M. Cerio, JR.
IPC分类号： C23C14/34
CPC分类号： C23C14/0641 , C23C14/358 , H01J37/321 , H01J37/3426
摘要： A method for depositing a metal-containing film on a substrate using an inductively coupled (ICP) physical vapor deposition (PVD) system. The ICP PVD deposition is performed under process conditions that thermalize neutral sputtered metal atoms by collisions with a process gas and minimize or eliminate exposure of ions to the substrate.
摘要翻译：一种使用电感耦合（ICP）物理气相沉积（PVD）系统在基片上沉积含金属膜的方法。 ICP PVD沉积在通过与工艺气体碰撞来热化中性溅射金属原子的工艺条件下进行，并最小化或消除离子暴露于衬底。

2. 发明申请

US20090321247A1 IONIZED PHYSICAL VAPOR DEPOSITION (iPVD) PROCESS 审中-公开
标题翻译：离子体蒸气沉积（iPVD）过程
公开(公告)号：US20090321247A1
公开(公告)日：2009-12-31
申请号：US12555068
申请日：2009-09-08
申请人： Frank M. Cerio, JR. , Jacques Faguet , Bruce D. Gittleman , Rodney L. Robison
发明人： Frank M. Cerio, JR. , Jacques Faguet , Bruce D. Gittleman , Rodney L. Robison
IPC分类号： C23C14/34
CPC分类号： C23C14/025 , C23C14/046 , C23C14/345 , C23C14/3492 , H01J37/32706 , H01J2237/3327 , H01L21/2855 , H01L21/76843 , H01L21/76865
摘要： A method is provided of operating a deposition system to deposit coating material into high aspect ratio nano-sized features on a patterned substrate that enhances sidewall coverage compared to field area and bottom surface coverage while minimizing or eliminating overhang. The method includes performing a process step with a gross field area deposition rate of about 25 to 70 nm/min and simultaneously etching the barrier layer to establish a net field area deposition rate of about 5 to 40 nm/min. The method may also include first performing a protective layer deposition step with a field area deposition rate of about 5 to 20 nm/min without etching the underlying surface then performing a surface modification step with gross deposition and simultaneous etching at a field modification net deposition rate of about −10 to +40 nm/min.
摘要翻译：提供了一种操作沉积系统以将涂层材料沉积在图案化衬底上的高纵横比纳米尺寸特征的方法，其增强了与场面积和底面覆盖率相比较，同时最小化或消除悬垂的侧壁覆盖。该方法包括执行总场积淀积速率为约25至70nm / min的工艺步骤，同时蚀刻阻挡层以建立约5至40nm / min的净场致积率。该方法还可以包括首先执行具有大约5至20nm / min的场区沉积速率的保护层沉积步骤，而不蚀刻下面的表面，然后在场修正网沉积速率下进行总沉积和同时蚀刻的表面改性步骤约-10至+ 40nm / min。

3. 发明申请

US20100015798A1 METHOD FOR FORMING A RUTHENIUM METAL CAP LAYER 有权
标题翻译：形成金属金属层的方法
公开(公告)号：US20100015798A1
公开(公告)日：2010-01-21
申请号：US12173814
申请日：2008-07-15
申请人： Kenji Suzuki , Frank M. Cerio, JR. , Miho Jomen , Shigeru Mizuno , Yasushi Mizusawa , Tadahiro Ishizaka
发明人： Kenji Suzuki , Frank M. Cerio, JR. , Miho Jomen , Shigeru Mizuno , Yasushi Mizusawa , Tadahiro Ishizaka
IPC分类号： H01L21/4763
CPC分类号： H01L21/76849 , C23C16/02 , C23C16/16 , H01L21/02068 , H01L21/28562 , H01L21/32134 , H01L21/32135 , H01L21/76826 , H01L21/76828 , H01L21/76834 , H01L21/76846 , H01L21/76856 , H01L21/76868 , H01L21/76883
摘要： A method for integrating ruthenium (Ru) metal cap layers and modified Ru metal cap layers into copper (Cu) metallization of semiconductor devices to improve electromigration (EM) and stress migration (SM) in bulk Cu metal. In one embodiment, the method includes providing a planarized patterned substrate containing a Cu metal surface and a dielectric layer surface, depositing first Ru metal on the Cu metal surface, and depositing additional Ru metal on the dielectric layer surface, where the amount of the additional Ru metal is less than the amount of the first Ru metal. The method further includes at least substantially removing the additional Ru metal from the dielectric layer surface to improve the selective formation of a Ru metal cap layer on the Cu metal surface. Other embodiments further include incorporating one or more types of modifier elements into the dielectric layer surface, the Cu metal surface, the Ru metal cap layer, or a combination thereof.
摘要翻译：将钌（Ru）金属盖层和改性的Ru金属覆盖层整合到半导体器件的铜（Cu）金属化中以改善块状Cu金属中的电迁移（EM）和应力迁移（SM）的方法。在一个实施例中，该方法包括提供包含Cu金属表面和电介质层表面的平坦化图案化衬底，在Cu金属表面上沉积第一Ru金属，以及在电介质层表面上沉积额外的Ru金属，其中额外的量 Ru金属少于第一Ru金属的量。该方法还包括从电介质层表面至少基本上去除额外的Ru金属，以改善在Cu金属表面上的Ru金属覆盖层的选择性形成。其他实施例还包括将一种或多种类型的改性剂元素结合到电介质层表面，Cu金属表面，Ru金属覆盖层或其组合中。

4. 发明申请

US20110076390A1 METHODS FOR MULTI-STEP COPPER PLATING ON A CONTINUOUS RUTHENIUM FILM IN RECESSED FEATURES 有权
标题翻译：在连续的连续薄膜上进行多步铜镀层的方法
公开(公告)号：US20110076390A1
公开(公告)日：2011-03-31
申请号：US12571162
申请日：2009-09-30
申请人： Frank M. Cerio, JR. , Shigeru Mizuno , Jonathan Reid , Thomas Ponnuswamy
发明人： Frank M. Cerio, JR. , Shigeru Mizuno , Jonathan Reid , Thomas Ponnuswamy
IPC分类号： B05D5/00 , B05D7/22 , C25D5/02
CPC分类号： C23C18/165 , C23C18/161 , C23C18/1651 , C23C18/1692 , C23C18/38 , C25D5/02 , C25D5/10 , C25D5/38 , C25D5/50 , H01L21/28556 , H01L21/2885 , H01L21/76843 , H01L21/76877 , H01L21/76883
摘要： Methods are provided for multi-step Cu metal plating on a continuous Ru metal film in recessed features found in advanced integrated circuits. The use of a continuous Ru metal film prevents formation of undesirable micro-voids during Cu metal filling of high-aspect-ratio recessed features, such as trenches and vias, and enables formation of large Cu metal grains that include a continuous Cu metal layer plated onto the continuous Ru metal film. The large Cu grains lower the electrical resistivity of the Cu filled recessed features and increase the reliability of the integrated circuit.
摘要翻译：提供了在先进集成电路中发现的凹陷特征中的连续Ru金属膜上的多步Cu金属电镀方法。使用连续的Ru金属膜可防止在高纵横比凹陷特征（例如沟槽和通孔）的Cu金属填充期间形成不期望的微孔，并且能够形成大的Cu金属晶粒，其包括连续的Cu金属层电镀到连续的Ru金属膜上。大的Cu晶粒降低了Cu填充凹陷特征的电阻率，增加了集成电路的可靠性。

5. 发明申请

US20110212274A1 HYBRID IN-SITU DRY CLEANING OF OXIDIZED SURFACE LAYERS 有权
标题翻译：氧化表面层的混合干燥清洁
公开(公告)号：US20110212274A1
公开(公告)日：2011-09-01
申请号：US12714152
申请日：2010-02-26
申请人： Adam Selsley , Frank M. Cerio, JR.
发明人： Adam Selsley , Frank M. Cerio, JR.
IPC分类号： B05D3/10
CPC分类号： C23C14/5826
摘要： According to one embodiment, the method includes providing a substrate containing a metal-containing barrier layer having an oxidized surface layer, exposing the oxidized surface layer to a flow of a first process gas containing plasma-excited argon gas to activate the oxidized surface layer and applying substrate bias power during the exposing of the oxidized surface layer to the flow of the first process gas. The method further includes exposing the activated oxidized surface layer to a second process gas containing non-plasma-excited hydrogen gas, wherein the exposure to the first process gas, in addition to activating the oxidized surface layer, facilitates chemical reduction of the activated oxidized surface layer by the second process gas containing the hydrogen gas. A thickness of the metal-containing barrier layer is not substantially changed by the hybrid in-situ dry cleaning process.
摘要翻译：根据一个实施方案，该方法包括提供含有含氧化表面层的含金属阻挡层的基材，将氧化表面层暴露于含有等离子体激发的氩气的第一工艺气体的流动以活化氧化的表面层;以及在将氧化的表面层暴露于第一工艺气体的流动期间施加衬底偏置功率。该方法还包括将活化的氧化表面层暴露于含有非等离子体激发的氢气的第二工艺气体，其中暴露于第一工艺气体除了活化氧化的表面层之外，还促进活化的氧化表面的化学还原通过含有氢气的第二工艺气体层。通过混合原位干洗方法，实质上不能改变含金属阻挡层的厚度。

6. 发明申请

US20090191721A1 SEQUENTIAL TANTALUM-NITRIDE DEPOSITION 失效
标题翻译：顺序硝酸盐沉积
公开(公告)号：US20090191721A1
公开(公告)日：2009-07-30
申请号：US12018813
申请日：2008-01-24
申请人： Frank M. Cerio, JR. , Shigeru Mizuno , Tsukasa Matsuda , Adam Selsey
发明人： Frank M. Cerio, JR. , Shigeru Mizuno , Tsukasa Matsuda , Adam Selsey
IPC分类号： H01L21/31
CPC分类号： H01L21/76843 , C23C14/046 , C23C14/32 , C23C14/541 , H01L21/2855 , H01L21/76846 , H01L21/76865
摘要： An iPVD system is programmed to deposit uniform material, such as barrier material, into high aspect ratio nano-size features on semiconductor substrates using a multi-step process within a vacuum chamber which enhances the sidewall coverage compared to the field and bottom coverage(s) while minimizing or eliminating overhang.
摘要翻译： iPVD系统被编程为在真空室内使用多步骤的方法将均匀的材料（例如阻挡材料）沉积在半导体衬底上的高纵横比纳米尺寸特征中，这增强了与场和底部覆盖（s ）同时最小化或消除突出。

7. 发明申请

US20100248473A1 SELECTIVE DEPOSITION OF METAL-CONTAINING CAP LAYERS FOR SEMICONDUCTOR DEVICES 有权
标题翻译：用于半导体器件的金属包层的选择性沉积
公开(公告)号：US20100248473A1
公开(公告)日：2010-09-30
申请号：US12414917
申请日：2009-03-31
申请人： Tadahiro Ishizaka , Shigeru Mizuno , Satohiko Hoshino , Hiroyuki Nagai , Yuki Chiba , Frank M. Cerio, JR.
发明人： Tadahiro Ishizaka , Shigeru Mizuno , Satohiko Hoshino , Hiroyuki Nagai , Yuki Chiba , Frank M. Cerio, JR.
IPC分类号： H01L21/768 , H01L21/3205
CPC分类号： H01L21/76849 , H01L21/02063 , H01L21/02074 , H01L21/3105 , H01L21/76814 , H01L21/76826 , H01L21/76828 , H01L21/76846 , H01L21/76856 , H01L21/76859 , H01L21/76883
摘要： A method for integrating metal-containing cap layers into copper (Cu) metallization of semiconductor devices. In one embodiment, the method includes providing a patterned substrate containing metal surfaces and dielectric layer surfaces, and modifying the dielectric layer surfaces by exposure to a reactant gas containing a hydrophobic functional group, where the modifying substitutes a hydrophilic functional group in the dielectric layer surfaces with a hydrophobic functional group. The method further includes depositing metal-containing cap layers selectively on the metal surfaces by exposing the modified dielectric layer surfaces and the metal surfaces to a deposition gas containing metal-containing precursor vapor.
摘要翻译：一种用于将含金属盖层整合到半导体器件的铜（Cu）金属化中的方法。在一个实施例中，该方法包括提供含有金属表面和电介质层表面的图案化衬底，以及通过暴露于含有疏水官能团的反应气体来修饰电介质层表面，其中修饰取代介电层表面中的亲水性官能团具有疏水官能团。该方法还包括通过将改性的介电层表面和金属表面暴露于含有金属的前体蒸气的沉积气体中，将金属含有的盖层选择性地沉积在金属表面上。

8. 发明申请

US20100029078A1 METHOD OF FORMING SEMICONDUCTOR DEVICES CONTAINING METAL CAP LAYERS 有权
公开(公告)号：US20100029078A1
公开(公告)日：2010-02-04
申请号：US12369376
申请日：2009-02-11
申请人： Noel Russell , Frank M. Cerio, JR. , Gregory Herdt
发明人： Noel Russell , Frank M. Cerio, JR. , Gregory Herdt
IPC分类号： H01L21/02
CPC分类号： H01L23/53238 , C23C14/04 , C23C14/14 , C23C14/5833 , C23C14/5846 , C23C16/04 , C23C16/06 , C23C16/56 , H01J2237/0812 , H01L21/02074 , H01L21/76825 , H01L21/76849 , H01L21/76859 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of methods for improving electrical leakage performance and minimizing electromigration in semiconductor devices containing metal cap layers are generally described herein. According to one embodiment, a method of forming a semiconductor device includes planarizing a top surface of a workpiece to form a substantially planar surface with conductive paths and dielectric regions, forming metal cap layers on the conductive paths, and exposing the top surface of the workpiece to a dopant source from a gas cluster ion beam (GCIB) to form doped metal cap layers on the conductive paths and doped dielectric layers on the dielectric regions. According to some embodiments the metal cap layers and the doped metal cap layers contain a noble metal selected from Pt, Au, Ru, Rh, Ir, and Pd.

9. 发明申请

US20110244680A1 SURFACE CLEANING AND SELECTIVE DEPOSITION OF METAL-CONTAINING CAP LAYERS FOR SEMICONDUCTOR DEVICES 有权
标题翻译：用于半导体器件的金属含有层的表面清洁和选择性沉积
公开(公告)号：US20110244680A1
公开(公告)日：2011-10-06
申请号：US12749782
申请日：2010-03-30
申请人： Kazuhito Tohnoe , Frank M. Cerio, JR.
发明人： Kazuhito Tohnoe , Frank M. Cerio, JR.
IPC分类号： H01L21/3205
CPC分类号： H01L21/67207 , H01L21/02074 , H01L21/3105 , H01L21/67184 , H01L21/76826 , H01L21/76828 , H01L21/7684 , H01L21/76849 , H01L21/76883
摘要： A method is provided for integrating metal-containing cap layers into copper (Cu) metallization of semiconductor devices. In one embodiment, the method includes providing a planarized patterned substrate containing metal surfaces and dielectric layer surfaces with a residue formed thereon, removing the residue from the planarized patterned substrate, and depositing metal-containing cap layers selectively on the metal surfaces by exposing the dielectric layer surfaces and the metal surfaces to a deposition gas containing metal-containing precursor vapor. The removing includes treating the planarized patterned substrate containing the residue with a reactant gas containing a hydrophobic functional group, and exposing the treated planarized patterned substrate to a reducing gas.
摘要翻译：提供了一种用于将含金属盖层整合到半导体器件的铜（Cu）金属化中的方法。在一个实施例中，该方法包括提供包含金属表面和介电层表面的平坦化图案化衬底，其上形成有残留物，从平坦化图案化衬底去除残余物，以及通过暴露电介质来选择性地沉积在金属表面上的含金属盖层层表面和金属表面到含有含金属的前体蒸气的沉积气体。除去包括用含有疏水性官能团的反应气体处理含有残余物的平坦化图案化衬底，以及将经处理的平坦化图案化衬底暴露于还原气体。

10. 发明申请

US20100081274A1 METHOD FOR FORMING RUTHENIUM METAL CAP LAYERS 审中-公开
标题翻译：形成金属箔层的方法
公开(公告)号：US20100081274A1
公开(公告)日：2010-04-01
申请号：US12240894
申请日：2008-09-29
申请人： Tadahiro Ishizaka , Shigeru Mizuno , Frank M. Cerio, JR.
发明人： Tadahiro Ishizaka , Shigeru Mizuno , Frank M. Cerio, JR.
IPC分类号： H01L21/4763
CPC分类号： H01L21/76814 , C23C16/0236 , C23C16/16 , H01L21/02063 , H01L21/02074 , H01L21/3105 , H01L21/76826 , H01L21/7684 , H01L21/76843 , H01L21/76849 , H01L21/76864
摘要： A method is provided for integrating ruthenium (Ru) metal deposition into manufacturing of semiconductor devices to improve electromigration and stress migration in copper (Cu) metal. Embodiments of the invention include treating patterned substrates containing metal layers and low-k dielectric materials with NHx (x≦3) radicals and H radicals to improve selective formation of ruthenium (Ru) metal cap layers on the metal layers relative to the low-k dielectric materials.
摘要翻译：提供了一种用于将钌（Ru）金属沉积物集成到半导体器件的制造中以改善铜（Cu）金属中的电迁移和应力迁移的方法。本发明的实施方案包括处理包含金属层和低k电介质材料的图案化衬底，其具有NH x（x和n L e 3）基团和H基团以改善相对于低k的金属层上钌（Ru）金属帽层的选择性形成介电材料。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式