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1. 发明授权

US06169030A Metallization process and method 失效
标题翻译：金属化过程和方法
公开(公告)号：US06169030A
公开(公告)日：2001-01-02
申请号：US09007233
申请日：1998-01-14
申请人： Mehul B. Naik , Ted Guo , Liang-Yuh Chen , Roderick Craig Mosely , Israel Beinglass
发明人： Mehul B. Naik , Ted Guo , Liang-Yuh Chen , Roderick Craig Mosely , Israel Beinglass
IPC分类号： H01L2144
CPC分类号： C23C14/32 , C23C14/025 , C23C14/046 , H01L21/2855 , H01L21/76877
摘要： The invention generally provides an improved process for providing uniform step coverage on a substrate and planarization of metal layers to form continuous, void-free interconnections in high aspect ratio, sub-half micron applications. The invention provides a multi-step PVD process in which the plasma power is varied for each of the steps to obtain favorable fill characteristics as well as good reflectivity, morphology and throughput. The initial plasma powers are relatively low to ensure good, void-free filling of the aperture and, then, the plasma powers are increased to obtain the desired reflectivity and morphology characteristics. The invention provides an aperture filling process comprising physical vapor depositing a metal over the substrate and varying the plasma power during the physical vapor deposition. Preferably, the plasma power is varied from a first discrete low plasma power to a second discrete high plasma power. Even more preferably, the plasma power is varied from a first discrete low plasma power to a second discrete low plasma power to a third discrete high plasma power.
摘要翻译：本发明通常提供了一种改进的方法，用于在衬底上提供均匀的台阶覆盖和金属层的平坦化，以在高纵横比，半微米应用中形成连续的无空隙互连。本发明提供了一种多步骤PVD工艺，其中等离子体功率对于每个步骤而言是变化的，以获得良好的填充特性以及良好的反射率，形态和产量。初始等离子体功率相对较低，以确保孔的良好的无空隙填充，然后增加等离子体功率以获得期望的反射率和形态特征。本发明提供一种孔填充方法，其包括在物理气相沉积中物理气相沉积衬底上的金属并改变等离子体功率。优选地，等离子体功率从第一离散低等离子体功率变化到第二离散高等离子体功率。更优选地，等离子体功率从第一离散低等离子体功率变化到第二离散低等离子体功率到第三离散高等离子体功率。

2. 发明授权

US06430458B1 Semi-selective chemical vapor deposition 失效
标题翻译：半选择性化学气相沉积
公开(公告)号：US06430458B1
公开(公告)日：2002-08-06
申请号：US09371617
申请日：1999-08-10
申请人： Roderick Craig Mosely , Liang-Yuh Chen , Ted Guo
发明人： Roderick Craig Mosely , Liang-Yuh Chen , Ted Guo
IPC分类号： B05D114
CPC分类号： H01L21/76864 , H01L21/76843 , H01L21/76876 , H01L21/76877 , H01L2221/1089 , Y10S977/891
摘要： The present invention is an apparatus and method for semi-selectively depositing a material on a substrate by chemical vapor deposition to form continuous, void-free contact holes or vias in sub-half micron applications. An insulating layer is preferentially deposited on the field of a substrate to delay or inhibit nucleation of metal on the field. A CVD metal is then deposited onto the substrate and grows selectively in the contact hole or via where a barrier layer serves as a nucleation layer. The process is preferably carried out in a multi-chamber system that includes both PVD and CVD processing chambers so that once the substrate is introduced into a vacuum environment, the filling of contact holes and vias occurs without the formation of an oxide layer on a patterned substrate.
摘要翻译：本发明是一种用于通过化学气相沉积在衬底上半选择性沉积材料以在半微米应用中形成连续的无空隙接触孔或通孔的装置和方法。绝缘层优先沉积在衬底的场上以延迟或抑制场上金属的成核。然后将CVD金属沉积到衬底上并选择性地生长在接触孔中，或通过其中阻挡层用作成核层。该方法优选在包括PVD和CVD处理室的多室系统中进行，使得一旦将基底引入真空环境中，接触孔和通孔的填充发生，而在图案上没有形成氧化物层基质。

3. 发明授权

US06743714B2 Low temperature integrated metallization process and apparatus 失效
公开(公告)号：US06743714B2
公开(公告)日：2004-06-01
申请号：US10074938
申请日：2002-02-11
申请人： Roderick Craig Mosely , Hong Zhang , Fusen Chen , Ted Guo , Liang-Yuh Chen
发明人： Roderick Craig Mosely , Hong Zhang , Fusen Chen , Ted Guo , Liang-Yuh Chen
IPC分类号： H01L2144
CPC分类号： H01L21/76876 , C23C14/568 , C23C16/54 , H01L21/32051 , H01L21/76843 , H01L21/76877 , H01L21/76879
摘要： The present invention relates generally to an improved process for providing uniform step coverage on a substrate and planarization of metal layers to form continuous, void-free contacts or vias in sub-half micron applications. In one aspect of the invention, a refractory layer is deposited onto a substrate having high aspect ratio contacts or vias formed thereon. A CVD metal layer is then deposited onto the refractory layer at low temperatures to provide a conformal wetting layer for a PVD metal. Next, a PVD metal is deposited onto the previously formed CVD metal layer at a temperature below that of the melting point temperature of the metal. The resulting CVD/PVD metal layer is substantially void-free. The metallization process is preferably carried out in an integrated processing system that includes both a PVD and CVD processing chamber so that once the substrate is introduced into a vacuum environment, the metallization of the vias and contacts occurs without the formation of an oxide layer over the CVD Al layer.

4. 发明授权

US6080665A Integrated nitrogen-treated titanium layer to prevent interaction of titanium and aluminum 失效
标题翻译：集成的氮处理钛层，以防止钛和铝的相互作用
公开(公告)号：US6080665A
公开(公告)日：2000-06-27
申请号：US840209
申请日：1997-04-11
申请人： Liang-Yuh Chen , Ted Guo , Roderick Craig Mosely
发明人： Liang-Yuh Chen , Ted Guo , Roderick Craig Mosely
IPC分类号： H01L21/28 , C23C14/14 , C23C14/58 , C23C16/06 , C23C16/56 , H01L21/203 , H01L21/3205 , H01L21/768 , H01L21/44
CPC分类号： C23C14/5826 , C23C14/14 , C23C14/586 , C23C16/06 , C23C16/56 , H01L21/76843 , H01L21/76856 , H01L21/76876 , H01L21/76877
摘要： The present invention generally provides a method for processing a substrate having exposed surfaces of titanium and/or silicon prior to deposition of aluminum. The substrate is positioned adjacent a process zone which provides a nitrogen plasma so that exposed areas of titanium and silicon on the substrate are stuffed with nitrogen to form titanium nitride (TiN) and various compounds of silicon and nitrogen (Si.sub.x N.sub.y), respectively. The nitrogen treated surfaces, i.e, TiN and silicon/nitrogen compounds, are resistant to interaction with aluminum. In this manner, the formation of electrically insulating TiAl.sub.3 and/or the spiking of silicon is reduced or eliminated.
摘要翻译：本发明通常提供一种在沉积铝之前处理具有钛和/或硅的暴露表面的衬底的方法。衬底位于提供氮等离子体的工艺区域附近，使得衬底上的钛和硅的暴露区域填充氮气，以分别形成氮化钛（TiN）和各种硅和氮化合物（SixNy）。氮处理的表面即TiN和硅/氮化合物对铝的相互作用具有抗性。以这种方式，减少或消除了电绝缘TiAl 3的形成和/或硅的尖峰。

5. 发明授权

US06207222B1 Dual damascene metallization 失效
标题翻译：双镶嵌金属化
公开(公告)号：US06207222B1
公开(公告)日：2001-03-27
申请号：US09379696
申请日：1999-08-24
申请人： Liang-Yuh Chen , Rong Tao , Ted Guo , Roderick Craig Mosely
发明人： Liang-Yuh Chen , Rong Tao , Ted Guo , Roderick Craig Mosely
IPC分类号： B05D512
CPC分类号： H01L21/76843 , H01L21/76807 , H01L21/76831 , H01L21/76862 , H01L21/76876 , H01L21/76877
摘要： The present invention generally provides a metallization process for forming a highly integrated interconnect. More particularly, the present invention provides a dual damascene interconnect module that incorporates a barrier layer deposited on all exposed surface of a dielectric layer which contains a dual damascene via and wire definition. A conductive metal is deposited on the barrier layer using two or more deposition methods to fill the via and wire definition prior to planarization. The invention provides the advantages of having copper wires with lower resistivity (greater conductivity) and greater electromigration resistance than aluminum, a barrier layer between the copper wire and the surrounding dielectric material, void-free, sub-half micron selective CVD Al via plugs, and a reduced number of process steps to achieve such integration.
摘要翻译：本发明通常提供用于形成高度集成的互连件的金属化工艺。更具体地，本发明提供了一种双镶嵌互连模块，其包含沉积在包含双镶嵌通孔和线定义的电介质层的所有暴露表面上的阻挡层。在平坦化之前，使用两种或更多种沉积方法在阻挡层上沉积导电金属以填充通孔和导线的定义。本发明提供了具有比铝更低的电阻率（更大的导电性）和更大的电迁移电阻的铜线，铜线和周围介电材料之间的阻挡层，无空隙的半微米选择性CVD Al通过插塞的优点，并减少了实现这种集成的流程步骤。

6. 发明授权

US6139905A Integrated CVD/PVD Al planarization using ultra-thin nucleation layers 失效
标题翻译：使用超薄成核层的集成CVD / PVD Al平面化
公开(公告)号：US6139905A
公开(公告)日：2000-10-31
申请号：US838839
申请日：1997-04-11
申请人： Liang-Yuh Chen , Mehul Naik , Ted Guo , Roderick Craig Mosely
发明人： Liang-Yuh Chen , Mehul Naik , Ted Guo , Roderick Craig Mosely
IPC分类号： H01L21/28 , H01L21/203 , H01L21/3205 , H01L21/768 , B05D5/12
CPC分类号： H01L21/28556 , H01J37/32082 , H01L21/288 , H01L21/76843 , H01L21/76871 , H01L21/76876 , H01L21/76877
摘要： The present invention provides a method and apparatus for forming an interconnect with application in small feature sizes (such as quarter micron widths) having high aspect ratios. Generally, the present invention provides a method and apparatus for depositing a wetting layer for subsequent physical vapor deposition to fill the interconnect. In one aspect of the invention, the wetting layer is a metal layer deposited using either CVD techniques or electroplating, such as CVD aluminum (Al). The wetting layer is nucleated using an ultra-thin layer, denoted as .di-elect cons. layer, as a nucleation layer. The .di-elect cons. layer is preferably comprised of a material such as Ti, TiN, Al, Ti/TiN, Ta, TaN, Cu, a flush of TDMAT or the like. The .di-elect cons. layer may be deposited using PVD or CVD techniques, preferably PVD techniques to improve film quality and orientation within the feature. Contrary to conventional wisdom, the .di-elect cons. layer is not continuous to nucleate the growth of the CVD wetting layer thereon. A PVD deposited metal is then deposited on the wetting layer at low temperature to fill the interconnect.
摘要翻译：本发明提供一种用于形成具有高纵横比的小特征尺寸（例如四分之一微米宽度）的互连的方法和装置。通常，本发明提供了一种用于沉积用于后续物理气相沉积以润湿互连的润湿层的方法和装置。在本发明的一个方面，润湿层是使用CVD技术或电镀（诸如CVD铝（Al））沉积的金属层。润湿层使用表示为+531层的超薄层作为成核层成核。 +531层优选由诸如Ti，TiN，Al，Ti / TiN，Ta，TaN，Cu的材料，TDMAT等的齐平构成。可以使用PVD或CVD技术沉积+531层，优选PVD技术以改善特征内的膜质量和取向。与常规智慧相反，+531层不连续以使其上的CVD润湿层的生长成核。然后在低温下将PVD沉积的金属沉积在润湿层上以填充互连。

7. 发明授权

US6139697A Low temperature integrated via and trench fill process and apparatus 失效
标题翻译：低温集成通孔和沟槽填充工艺和设备
公开(公告)号：US6139697A
公开(公告)日：2000-10-31
申请号：US792292
申请日：1997-01-31
申请人： Liang-Yuh Chen , Roderick Craig Mosely , Fusen Chen , Rong Tao , Ted Guo
发明人： Liang-Yuh Chen , Roderick Craig Mosely , Fusen Chen , Rong Tao , Ted Guo
IPC分类号： H01L21/285 , H01L21/3205 , H01L21/768 , H01L23/52 , C23C14/34
CPC分类号： H01L21/76877
摘要： The present invention relates generally to an improved process for providing complete via fill on a substrate and planarization of metal layers to form continuous, void-free contacts or vias in sub-half micron applications. In one aspect of the invention, a refractory layer is deposited onto a substrate having high aspect ratio contacts or vias formed thereon. A CVD metal layer, such as CVD Al or CVD Cu, is then deposited onto the refractory layer at low temperatures to provide a conformal wetting layer for a PVD Cu. Next, a PVD Cu is deposited onto the previously formed CVD Cu layer at a temperature below that of the melting point temperature of the metal. The resulting CVD/PVD Cu layer is substantially void-free. The metallization process is preferably carried out in an integrated processing system that includes both a PVD and CVD processing chamber so that once the substrate is introduced into a vacuum environment, the metallization of the vias and contacts occurs without the formation of an oxide layer over the CVD Cu layer. The via fill process of the present invention is also successful with air-exposure between the CVD Cu and PVD Cu steps.
摘要翻译：本发明一般涉及在衬底上提供完整的通孔填充物和金属层的平坦化以在半微米应用中形成连续的无空隙触点或通孔的改进方法。在本发明的一个方面中，将耐火层沉积在具有高比例接触或在其上形成的通孔的基底上。然后将CVD金属层（例如CVD Al或CVD Cu）在低温下沉积到耐火层上，以提供用于PVD Cu的保形润湿层。接下来，在低于金属的熔点温度的温度下，将PVD Cu沉积在先前形成的CVD Cu层上。所得到的CVD / PVD Cu层基本上无空隙。金属化处理优选在包括PVD和CVD处理室的一体化处理系统中进行，使得一旦将衬底引入真空环境中，就会发生通孔和触点的金属化，而不会在其上形成氧化物层 CVD Cu层。本发明的通孔填充方法也可以在CVD Cu和PVD Cu步骤之间的空气曝光成功。

8. 发明授权

US6001420A Semi-selective chemical vapor deposition 失效
标题翻译：半选择性化学气相沉积
公开(公告)号：US6001420A
公开(公告)日：1999-12-14
申请号：US718656
申请日：1996-09-23
申请人： Roderick Craig Mosely , Liang-Yuh Chen , Ted Guo
发明人： Roderick Craig Mosely , Liang-Yuh Chen , Ted Guo
IPC分类号： C23C16/06 , H01L21/28 , H01L21/285 , H01L21/768 , B05D1/36 , C23C16/00
CPC分类号： H01L21/76864 , H01L21/76843 , H01L21/76876 , H01L21/76877 , H01L2221/1089 , Y10S977/891
摘要： The present invention is a method for semi-selectively depositing a material on a substrate by chemical vapor deposition to form continuous, void-free contact holes or vias in sub-half micron applications. An insulating layer is preferentially deposited on the field of a substrate to delay or inhibit nucleation of metal on the field. A CVD metal is then deposited onto the substrate and grows selectively in the contact hole or via where a barrier layer serves as a nucleation layer. The process is preferably carried out in a multi-chamber system that includes both PVD and CVD processing chambers so that once the substrate is introduced into a vacuum environment, the filling of contact holes and vias occurs without the formation of an oxide layer on a patterned substrate.
摘要翻译：本发明是通过化学气相沉积在衬底上半选择性沉积材料以在半微米应用中形成连续的无空隙接触孔或通孔的方法。绝缘层优先沉积在衬底的场上以延迟或抑制场上金属的成核。然后将CVD金属沉积到衬底上并选择性地生长在接触孔中，或通过其中阻挡层用作成核层。该方法优选在包括PVD和CVD处理室的多室系统中进行，使得一旦将基底引入真空环境中，接触孔和通孔的填充发生，而在图案上没有形成氧化物层基质。

9. 发明授权

US5989623A Dual damascene metallization 失效
标题翻译：双镶嵌金属化
公开(公告)号：US5989623A
公开(公告)日：1999-11-23
申请号：US914521
申请日：1997-08-19
申请人： Liang-Yuh Chen , Rong Tao , Ted Guo , Roderick Craig Mosely
发明人： Liang-Yuh Chen , Rong Tao , Ted Guo , Roderick Craig Mosely
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/52 , B05D5/12
CPC分类号： H01L21/76843 , H01L21/76831 , H01L21/76862 , H01L21/76876 , H01L21/76877 , H01L21/76807
摘要： The present invention generally provides a metallization process for forming a highly integrated interconnect. More particularly, the present invention provides a dual damascene interconnect module that incorporates a barrier layer deposited on all exposed surface of a dielectric layer which contains a dual damascene via and wire definition. A conductive metal is deposited on the barrier layer using two or more deposition methods to fill the via and wire definition prior to planarization. The invention provides the advantages of having copper wires with lower resistivity (greater conductivity) and greater electromigration resistance than aluminum, a barrier layer between the copper wire and the surrounding dielectric material, void-free, sub-half micron selective CVD Al via plugs, and a reduced number of process steps to achieve such integration.
摘要翻译：本发明通常提供用于形成高度集成的互连件的金属化工艺。更具体地，本发明提供了一种双镶嵌互连模块，其包含沉积在包含双镶嵌通孔和线定义的电介质层的所有暴露表面上的阻挡层。在平坦化之前，使用两种或更多种沉积方法在阻挡层上沉积导电金属以填充通孔和导线的定义。本发明提供了具有比铝更低的电阻率（更大的导电性）和更大的电迁移电阻的铜线，铜线和周围介电材料之间的阻挡层，无空隙的半微米选择性CVD Al通过插塞的优点，并减少了实现这种集成的流程步骤。

10. 发明授权

US5877087A Low temperature integrated metallization process and apparatus 失效
公开(公告)号：US5877087A
公开(公告)日：1999-03-02
申请号：US561605
申请日：1995-11-21
申请人： Roderick Craig Mosely , Hong Zhang , Fusen Chen , Ted Guo
发明人： Roderick Craig Mosely , Hong Zhang , Fusen Chen , Ted Guo
IPC分类号： H01L21/285 , C23C14/56 , C23C16/54 , H01L21/28 , H01L21/3205 , H01L21/677 , H01L21/768 , H01L21/441
CPC分类号： H01L21/76876 , C23C14/568 , C23C16/54 , H01L21/32051 , H01L21/76843 , H01L21/76877 , H01L21/76879
摘要： The present invention relates generally to an improved process for providing uniform step coverage on a substrate and planarization of metal layers to form continuous, void-free contacts or vias in sub-half micron applications. In one aspect of the invention, a refractory layer is deposited onto a substrate having high aspect ratio contacts or vias formed thereon. A CVD metal layer is then deposited onto the refractory layer at low temperatures to provide a conformal wetting layer for a PVD metal. Next, a PVD metal is deposited onto the previously formed CVD metal layer at a temperature below that of the melting point temperature of the metal. The resulting CVD/PVD metal layer is substantially void-free. The metallization process is preferably carried out in an integrated processing system that includes both a PVD and CVD processing chamber so that once the substrate is introduced into a vacuum environment, the metallization of the vias and contacts occurs without the formation of an oxide layer over the CVD Al layer.

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