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1. 发明授权

US09058180B2 Unified high-frequency out-of-order pick queue with support for triggering early issue of speculative instructions 有权
标题翻译：统一的高频无序拣选队列，支持触发早期发布的投机指令
公开(公告)号：US09058180B2
公开(公告)日：2015-06-16
申请号：US12493743
申请日：2009-06-29
申请人： Robert T. Golla , Matthew B. Smittle , Mark A. Luttrell , Xiang Shan Li
发明人： Robert T. Golla , Matthew B. Smittle , Mark A. Luttrell , Xiang Shan Li
IPC分类号： G06F15/00 , G06F9/30 , G06F9/40 , G06F9/38
CPC分类号： G06F9/3838 , G06F9/3842 , G06F9/3851 , G06F9/3855 , G06F9/3857
摘要： Systems and methods for efficient picking of instructions for out-of-order issue and execution in a processor. In one embodiment, a processor comprises a unified pick queue that is dynamically allocated. Each entry is configured to store age and dependency information relative to other decoded instructions. Also, each entry stores a picked field, which when asserted indicates the decoded instruction has already been picked for out-of-order issue and execution. When asserted, a trigger field indicates a result of a corresponding decoded instruction will be available a predetermined number of clock cycles afterward. A younger instruction dependent on a result of an older instruction is ready to be picked before the result of the older instruction is available. In this case, the older instruction has asserted picked and trigger fields.
摘要翻译：用于在处理器中有效挑选无序问题和执行指令的系统和方法。在一个实施例中，处理器包括动态分配的统一选择队列。每个条目被配置为存储相对于其他解码指令的年龄和依赖性信息。此外，每个条目存储拾取的字段，当被断言指示解码的指令已被选择用于无序发行和执行时。当被确认时，触发字段指示相应的解码指令的结果将在预定数量的时钟周期之后可用。在较老指令的结果可用之前，可以选择取决于旧指令结果的年轻指令。在这种情况下，较旧的指令已经断言了选择和触发字段。

2. 发明申请

US20100332804A1 UNIFIED HIGH-FREQUENCY OUT-OF-ORDER PICK QUEUE WITH SUPPORT FOR SPECULATIVE INSTRUCTIONS 有权
标题翻译：统一的高频无排序抽奖活动支持用于指导性说明
公开(公告)号：US20100332804A1
公开(公告)日：2010-12-30
申请号：US12493743
申请日：2009-06-29
申请人： Robert T. Golla , Matthew B. Smittle , Mark A. Luttrell , Xiang Shan Li
发明人： Robert T. Golla , Matthew B. Smittle , Mark A. Luttrell , Xiang Shan Li
IPC分类号： G06F9/30
CPC分类号： G06F9/3838 , G06F9/3842 , G06F9/3851 , G06F9/3855 , G06F9/3857
摘要： Systems and methods for efficient picking of instructions for out-of-order issue and execution in a processor. In one embodiment, a processor comprises a unified pick queue that is dynamically allocated. Each entry is configured to store age and dependency information relative to other decoded instructions. Also, each entry stores a picked field, which when asserted indicates the decoded instruction has already been picked for out-of-order issue and execution. When asserted, a trigger field indicates a result of a corresponding decoded instruction will be available a predetermined number of clock cycles afterward. A younger instruction dependent on a result of an older instruction is ready to be picked before the result of the older instruction is available. In this case, the older instruction has asserted picked and trigger fields.
摘要翻译：用于在处理器中有效挑选无序问题和执行指令的系统和方法。在一个实施例中，处理器包括动态分配的统一选择队列。每个条目被配置为存储相对于其他解码指令的年龄和依赖性信息。此外，每个条目存储拾取的字段，当被断言指示解码的指令已被选择用于无序发行和执行时。当被确认时，触发字段指示相应的解码指令的结果将在预定数量的时钟周期之后可用。在较老指令的结果可用之前，可以选择取决于旧指令结果的年轻指令。在这种情况下，较旧的指令已经断言了选择和触发字段。

3. 发明授权

US07747771B1 Register access protocol in a multihreaded multi-core processor 有权
标题翻译：在多线程多核处理器中注册访问协议
公开(公告)号：US07747771B1
公开(公告)日：2010-06-29
申请号：US10881178
申请日：2004-06-30
申请人： Manish Shah , Robert T. Golla , Mark A. Luttrell , Gregory F. Grohoski
发明人： Manish Shah , Robert T. Golla , Mark A. Luttrell , Gregory F. Grohoski
IPC分类号： G06F15/16 , G06F15/76 , G06F13/00
CPC分类号： G06F15/16
摘要： A method and mechanism for managing access to a plurality of registers in a processing device are contemplated. A processing device includes multiple nodes coupled to a ring bus, each of which include one or more registers which may be accessed by processes executing within the device. Also coupled to the ring bus is a ring control unit which is configured to initiate transactions targeted to nodes on the ring bus. Each of the nodes are configured receive and process bus transaction with a fixed latency whether or not the first transaction is targeted to the receiving node. The ring control unit is configured to periodically convey idle transactions on the ring bus in order to allow nodes responding to indeterminate transactions to gain access to the bus.
摘要翻译：考虑了用于管理对处理设备中的多个寄存器的访问的方法和机制。处理设备包括耦合到环形总线的多个节点，每个节点包括一个或多个可由设备内执行的进程访问的寄存器。还耦合到环形总线的环控制单元被配置为发起针对环形总线上的节点的事务。每个节点被配置为具有固定延迟的接收和处理总线事务，无论第一个事务是否针对接收节点。环控制单元被配置为周期性地传送环总线上的空闲事务，以便允许节点响应不确定的事务来访问总线。

4. 发明授权

US08099586B2 Branch misprediction recovery mechanism for microprocessors 有权
标题翻译：微处理器分支错误预测恢复机制
公开(公告)号：US08099586B2
公开(公告)日：2012-01-17
申请号：US12346349
申请日：2008-12-30
申请人： Yuan C. Chou , Robert T. Golla , Mark A. Luttrell , Paul J. Jordan , Manish Shah
发明人： Yuan C. Chou , Robert T. Golla , Mark A. Luttrell , Paul J. Jordan , Manish Shah
IPC分类号： G06F9/00
CPC分类号： G06F9/3844 , G06F9/3863
摘要： A system and method for reducing branch misprediction penalty. In response to detecting a mispredicted branch instruction, circuitry within a microprocessor identifies a predetermined condition prior to retirement of the branch instruction. Upon identifying this condition, the entire corresponding pipeline is flushed prior to retirement of the branch instruction, and instruction fetch is started at a corresponding address of an oldest instruction in the pipeline immediately prior to the flushing of the pipeline. The correct outcome is stored prior to the pipeline flush. In order to distinguish the mispredicted branch from other instructions, identification information may be stored alongside the correct outcome. One example of the predetermined condition being satisfied is in response to a timer reaching a predetermined threshold value, wherein the timer begins incrementing in response to the mispredicted branch detection and resets at retirement of the mispredicted branch.
摘要翻译：减少分支误判处罚的系统和方法。响应于检测到错误的分支指令，微处理器内的电路在退出分支指令之前识别预定的条件。在识别该条件之后，在分支指令退出之前将整个对应的流水线冲洗，并且在冲洗流水线之前在管道中的最早的指令的对应地址开始指令提取。在管道冲洗之前存储正确的结果。为了将错误预测的分支与其他指令区分开，识别信息可以与正确的结果一起存储。满足预定条件的一个示例是响应于定时器达到预定阈值，其中定时器响应于错误预测的分支检测而开始递增，并且在退出预测分支时重置。

5. 发明授权

US09665375B2 Mitigation of thread hogs on a threaded processor and prevention of allocation of resources to one or more instructions following a load miss 有权
公开(公告)号：US09665375B2
公开(公告)日：2017-05-30
申请号：US13457055
申请日：2012-04-26
申请人： Yuan C. Chou , Robert T. Golla , Mark A. Luttrell
发明人： Yuan C. Chou , Robert T. Golla , Mark A. Luttrell
IPC分类号： G06F9/312 , G06F9/38 , G06F9/50 , G06F9/30
CPC分类号： G06F9/3861 , G06F9/30043 , G06F9/3851 , G06F9/3867 , G06F9/50
摘要： Systems and methods for efficient thread arbitration in a threaded processor with dynamic resource allocation. A processor includes a resource shared by multiple threads. The resource includes an array with multiple entries, each of which may be allocated for use by any thread. Control logic detects a load miss to memory, wherein the miss is associated with a latency greater than a given threshold. The load instruction or an immediately younger instruction is selected for replay for an associated thread. A pipeline flush and replay for the associated thread begins with the selected instruction. Instructions younger than the load instruction are held at a given pipeline stage until the load instruction completes. During replay, this hold prevents resources from being allocated to the associated thread while the load instruction is being serviced.

6. 发明授权

US08301865B2 System and method to manage address translation requests 有权
标题翻译：管理地址转换请求的系统和方法
公开(公告)号：US08301865B2
公开(公告)日：2012-10-30
申请号：US12493941
申请日：2009-06-29
申请人： Gregory F. Grohoski , Paul J. Jordan , Mark A. Luttrell , Zeid Hartuon Samoail , Robert T. Golla
发明人： Gregory F. Grohoski , Paul J. Jordan , Mark A. Luttrell , Zeid Hartuon Samoail , Robert T. Golla
IPC分类号： G06F12/00 , G06F9/26 , G06F9/34
CPC分类号： G06F12/1027 , G06F2212/684
摘要： A system and method for servicing translation lookaside buffer (TLB) misses may manage separate input and output pipelines within a memory management unit. A pending request queue (PRQ) in the input pipeline may include an instruction-related portion storing entries for instruction TLB (ITLB) misses and a data-related portion storing entries for potential or actual data TLB (DTLB) misses. A DTLB PRQ entry may be allocated to each load/store instruction selected from the pick queue. The system may select an ITLB- or DTLB-related entry for servicing dependent on prior PRQ entry selection(s). A corresponding entry may be held in a translation table entry return queue (TTERQ) in the output pipeline until a matching address translation is received from system memory. PRQ and/or TTERQ entries may be deallocated when a corresponding TLB miss is serviced. PRQ and/or TTERQ entries associated with a thread may be deallocated in response to a thread flush.
摘要翻译：用于服务翻译后备缓冲器（TLB）的系统和方法可以管理存储器管理单元内的单独的输入和输出管线。输入流水线中的未决请求队列（PRQ）可以包括存储用于指令TLB（ITLB）未命中的条目的指令相关部分和存储潜在或实际数据TLB（DTLB）丢失的条目的数据相关部分。可以将DTLB PRQ条目分配给从拾取队列中选择的每个加载/存储指令。系统可以根据先前的PRQ条目选择来选择与ITLB或DTLB相关的条目进行服务。相应的条目可以保存在输出流水线中的转换表条目返回队列（TTERQ）中，直到从系统存储器接收到匹配的地址转换。当服务对应的TLB未命中时，PRQ和/或TTERQ条目可以被释放。与线程相关联的PRQ和/或TTERQ条目可以响应于线程刷新而被释放。

7. 发明申请

US20100169611A1 BRANCH MISPREDICTION RECOVERY MECHANISM FOR MICROPROCESSORS 有权
标题翻译：用于微处理器的分支机构故障恢复机制
公开(公告)号：US20100169611A1
公开(公告)日：2010-07-01
申请号：US12346349
申请日：2008-12-30
申请人： Yuan C. Chou , Robert T. Golla , Mark A. Luttrell , Paul J. Jordan , Manish Shah
发明人： Yuan C. Chou , Robert T. Golla , Mark A. Luttrell , Paul J. Jordan , Manish Shah
IPC分类号： G06F9/312
CPC分类号： G06F9/3844 , G06F9/3863
摘要： A system and method for reducing branch misprediction penalty. In response to detecting a mispredicted branch instruction, circuitry within a microprocessor identifies a predetermined condition prior to retirement of the branch instruction. Upon identifying this condition, the entire corresponding pipeline is flushed prior to retirement of the branch instruction, and instruction fetch is started at a corresponding address of an oldest instruction in the pipeline immediately prior to the flushing of the pipeline. The correct outcome is stored prior to the pipeline flush. In order to distinguish the mispredicted branch from other instructions, identification information may be stored alongside the correct outcome. One example of the predetermined condition being satisfied is in response to a timer reaching a predetermined threshold value, wherein the timer begins incrementing in response to the mispredicted branch detection and resets at retirement of the mispredicted branch.
摘要翻译：减少分支误判处罚的系统和方法。响应于检测到错误的分支指令，微处理器内的电路在退出分支指令之前识别预定的条件。在识别该条件之后，在分支指令退出之前将整个对应的流水线冲洗，并且在冲洗流水线之前在管道中的最早的指令的对应地址开始指令提取。在管道冲洗之前存储正确的结果。为了将错误预测的分支与其他指令区分开，识别信息可以与正确的结果一起存储。满足预定条件的一个示例是响应于定时器达到预定阈值，其中定时器响应于错误预测的分支检测而开始递增，并且在退出预测分支时重置。

8. 发明授权

US07509484B1 Handling cache misses by selectively flushing the pipeline 有权
标题翻译：通过选择性地冲洗管道来处理高速缓存未命中
公开(公告)号：US07509484B1
公开(公告)日：2009-03-24
申请号：US10882807
申请日：2004-06-30
申请人： Robert T. Golla , Mark A. Luttrell
发明人： Robert T. Golla , Mark A. Luttrell
IPC分类号： G06F9/30 , G06F9/40 , G06F9/00
CPC分类号： G06F9/3851 , G06F9/3802 , G06F9/3824 , G06F9/3826 , G06F9/3834 , G06F9/3861 , G06F9/3867
摘要： An apparatus and method for efficiently managing data cache load misses is described in connection with a multithreaded, pipelined multiprocessor chip. A CMT processor keeps track of load misses for each thread by issuing a load miss signal each time a load instruction to the data cache misses. A detection logic functionality in the IFU responds the load miss signal to determine if a valid instruction from the thread is at the one of the pipeline stages. If no instructions from the thread are detected in the pipeline, then no flush is required and the thread is placed in a wait state until the requested data is returned from higher order memory. If any instruction from the thread is detected in the pipeline, the thread is flushed and the instruction is re-fetched.
摘要翻译：结合多线程流水线多处理器芯片描述了一种有效管理数据高速缓存加载缺失的装置和方法。 CMT处理器通过在每次向数据高速缓存的加载指令未命中时发出加载未命中信号来跟踪每个线程的加载缺失。 IFU中的检测逻辑功能响应负载未命中信号以确定来自线程的有效指令是否处于流水线级中的一个。如果在流水线中没有检测到线程的指令，则不需要刷新，并且线程处于等待状态，直到从高阶存储器返回所请求的数据。如果在流水线中检测到线程中的任何指令，则刷新线程并重新读取指令。

9. 发明授权

US07519796B1 Efficient utilization of a store buffer using counters 有权
标题翻译：使用计数器高效利用存储缓冲区
公开(公告)号：US07519796B1
公开(公告)日：2009-04-14
申请号：US10881935
申请日：2004-06-30
申请人： Robert T. Golla , Mark A. Luttrell
发明人： Robert T. Golla , Mark A. Luttrell
IPC分类号： G06F9/00
CPC分类号： G06F9/3824 , G06F9/3814 , G06F9/3826 , G06F9/3842 , G06F9/3851 , G06F9/3857 , G06F9/3859 , G06F9/3867 , G06F9/3873
摘要： An apparatus and method for efficiently managing store buffer operations is described in connection with a multithreaded multiprocessor chip. A CMT processor keeps track of stores by maintaining two store counters in the instruction fetch unit (IFU). A speculative store counter in the IFU tracks stores in flight to the store buffer as well as stores already in the store buffer. A committed store counter in the IFU tracks the number of stores actually in the store buffer. The store buffer provides allocate and deallocate signals to accurately maintain the committed store counter. The IFU stops issuing stores to the store buffer once the speculative counter has reached a threshold value. Upon a flush, the IFU sets the speculative counter equal to the committed store counter. In this way, an efficient feedback mechanism is provided for preventing store buffer overflow that minimizes the store buffer size, operations time and power usage.
摘要翻译：结合多线程多处理器芯片描述用于有效管理存储缓冲器操作的装置和方法。 CMT处理器通过在指令获取单元（IFU）中维护两个存储计数器来跟踪存储。 IFU中的推测性商店计数器跟踪到商店缓冲区的商店，并且已经存储在商店缓冲区中。 IFU中提供的存储计数器跟踪实际在商店缓冲区中的商店数量。存储缓冲区提供分配和释放信号以准确地维护提交的存储计数器。一旦推测计数器达到阈值，IFU将停止向存储缓冲区发出存储。在刷新时，IFU将推测计数器设置为等于提交的存储计数器。以这种方式，提供了一种有效的反馈机制，用于防止存储缓冲区溢出，使存储缓冲区大小，操作时间和功率使用最小化。

10. 发明申请

US20130297910A1 MITIGATION OF THREAD HOGS ON A THREADED PROCESSOR USING A GENERAL LOAD/STORE TIMEOUT COUNTER 审中-公开
标题翻译：使用一般负载/存储超时计数器在螺纹加工器上减少螺纹头
公开(公告)号：US20130297910A1
公开(公告)日：2013-11-07
申请号：US13463319
申请日：2012-05-03
申请人： Jared C. Smolens , Robert T. Golla , Mark A. Luttrell , Paul J. Jordan
发明人： Jared C. Smolens , Robert T. Golla , Mark A. Luttrell , Paul J. Jordan
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3861 , G06F9/3851 , G06F9/5016 , G06F2209/507
摘要： Systems and methods for efficient thread arbitration in a threaded processor with dynamic resource allocation. A processor includes a resource shared by multiple threads. The resource includes entries which may be allocated for use by any thread. Control logic detects long latency instructions. Long latency instructions have a latency greater than a given threshold. One example is a load instruction that has a read-after-write (RAW) data dependency on a store instruction that misses a last-level data cache. The long latency instruction or an immediately younger instruction is selected for replay for an associated thread. A pipeline flush and replay for the associated thread begins with the selected instruction. Instructions younger than the long latency instruction are held at a given pipeline stage until the long latency instruction completes. During replay, this hold prevents resources from being allocated to the associated thread while the long latency instruction is being serviced.
摘要翻译：在具有动态资源分配的线程处理器中有效的线程仲裁的系统和方法。处理器包括由多个线程共享的资源。资源包括可以分配给任何线程使用的条目。控制逻辑检测长延迟指令。长延迟指令的延迟大于给定的阈值。一个示例是对于丢失最后一级数据高速缓存的存储指令具有对后读写（RAW）数据依赖性的加载指令。选择长延迟指令或立即更年轻的指令用于相关线程的重放。相关线程的流水线冲洗和重播将以所选指令开始。比长延迟指令更年轻的指令保持在给定的流水线阶段，直到长延迟指令完成。在重放期间，这种保持可以防止资源被分配给相关联的线程，而长时间延迟指令被服务。

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