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    • 1. 发明授权
    • Application-specific integrated circuits having programming functions
    • 具有可编程功能的专用集成电路
    • US5793656A
    • 1998-08-11
    • US268938
    • 1994-06-30
    • Robert L. RichmondRichard ClewerTheodore C. Hockey
    • Robert L. RichmondRichard ClewerTheodore C. Hockey
    • G06F15/78G06F17/10G06F7/38G05B23/02
    • G06F15/78G06F17/10
    • An application-specific integrated circuit (ASIC) for performing a selected one of a plurality of programmable functions on one or more input signals. The ASIC includes a plurality of component circuits (21-28), each for performing a predetermined component function (F.sub.1 -F.sub.8) on a signal supplied thereto, a plurality of component routers (31-36) for selectively coupling together the plurality of component circuits (21-28), and a control processor interface (40) for receiving control signals that control the plurality of component routers (31-36) such that selected component circuits (21-28) are coupled together in a manner by which the predetermined component functions (F.sub.1 -F.sub.8) of the selected component circuits are performed on the input signal in an order necessary to accomplish the selected one of the plurality of programmable functions. An application of the above-described circuit to a signal processing ASIC useful in stand-alone satellite modems is also disclosed.
    • 一种专用集成电路(ASIC),用于在一个或多个输入信号上执行多个可编程功能中选择的一个。 ASIC包括多个组件电路(21-28),每个组件电路用于对所提供的信号执行预定分量功能(F1-F8);多个组件路由器(31-36),用于选择性地将多个组件 电路(21-28)和控制处理器接口(40),用于接收控制多个组件路由器(31-36)的控制信号,使得所选择的组件电路(21-28)以下述方式耦合在一起: 按照完成所选择的多个可编程功能之一所需的顺序,对输入信号执行所选择的分量电路的预定分量函数(F1-F8)。 还公开了将上述电路应用于在独立卫星调制解调器中有用的信号处理ASIC。
    • 4. 发明授权
    • Symbol timing recovery using fir data interpolators
    • 使用fir数据插值器的符号定时恢复
    • US5524126A
    • 1996-06-04
    • US341891
    • 1994-11-15
    • Richard ClewerJanavikulam AnandkumarAndrew Macdonald
    • Richard ClewerJanavikulam AnandkumarAndrew Macdonald
    • H03H17/06H04L7/02H04L7/00
    • H04L7/0029H04L7/0334
    • A symbol timing recovery method and device which aligns the received data with a free-running symbol clock such that the aligned data sampling error is minimized. The symbol timing recovery process consists of detecting the timing phase error between the transmitters symbol clock and the receiver symbol clock, filtering the error, and then using the filtered error signal to control a block which changes the phase of the data relative to the timing reference signal. A data zero-crossing phase error detector drives a loop filter whose most significant bits form the address of the FIR coefficient ROM, which allows the FIR to interpolate data at sub-symbol resolution. The FIR coefficients are then used to synchronize the received data with the receiver clock.
    • 一种符号定时恢复方法和装置,其将所接收的数据与自由运行的符号时钟对准,使得对准的数据采样误差最小化。 符号定时恢复过程包括检测发射机符号时钟和接收机符号时钟之间的定时相位误差,对误差进行滤波,然后使用滤波后的误差信号来控制相对于定时参考改变数据相位的块 信号。 数据过零相位误差检测器驱动环路滤波器,其最高有效位形成FIR系数ROM的地址,这允许FIR以子符号分辨率内插数据。 然后使用FIR系数将接收的数据与接收机时钟同步。
    • 5. 发明授权
    • Method and device for estimating phase error
    • 用于估计相位误差的方法和装置
    • US5504453A
    • 1996-04-02
    • US323283
    • 1994-10-14
    • Andrew MacDonaldRichard ClewerJanavikulam Anandkumar
    • Andrew MacDonaldRichard ClewerJanavikulam Anandkumar
    • H04L27/227H04L27/22
    • H04L27/2273
    • A method and apparatus for use in estimating phase error in a phase-modulated carrier. The method and apparatus of the present invention may be embodied in a phase-error-estimator circuit which is typically incorporated into a demodulator of a digital communications receiver. In general, the phase-error-estimator circuit receives the I and Q components of a phase-modulated signal, and outputs an estimate of the phase error, if any, in the phase-modulated carrier signal associated with the received I and Q. Preferably, the phase-error-estimator circuit includes an index/polarity generator circuit coupled to a look-up table. The index/polarity generator receives I and Q and maps them onto a reduced range of phase angles represented by values X and Y. X and Y are fed to a reduced and substantially triangular look-up table which outputs the stored phase-error-estimate for the particular X and Y inputs.
    • 一种用于估计相位调制载波中的相位误差的方法和装置。 本发明的方法和装置可以体现在通常并入数字通信接收机的解调器中的相位误差估计器电路中。 通常,相位误差估计器电路接收相位调制信号的I分量和Q分量,并输出与所接收的I和Q相关联的相位调制载波信号中相位误差的估计(如果有的话)。 优选地,相位误差估计器电路包括耦合到查找表的索引/极性发生器电路。 索引/极性发生器接收I和Q并将它们映射到由值X和Y表示的相位角的减小的范围上.X和Y被馈送到减小且基本上三角形的查找表,其输出存储的相位误差估计 对于特定的X和Y输入。
    • 7. 发明授权
    • Method and apparatus for eliminating DC offset for digital I/Q
demodulators
    • 用于消除数字I / Q解调器的直流偏移的方法和装置
    • US5548244A
    • 1996-08-20
    • US339136
    • 1994-11-14
    • Richard Clewer
    • Richard Clewer
    • H03D3/00H03D7/16H03D1/00H04B1/26
    • H03D7/166H03D3/007H03D7/161
    • A method and apparatus utilizing the techniques of frequency shifting and filtering for converting an input signal having a desired signal at intermediate frequency and an undesired DC offset to a baseband frequency signal in which the undesired DC offset is eliminated. The apparatus includes a first multiplier for multiplying the input signal by a signal having substantially the same intermediate frequency plus an offset frequency (.DELTA.f) to produce a first output signal wherein the desired signal is shifted in frequency to the offset frequency (.DELTA.f) and the undesired DC offset is unaffected. The apparatus also includes a second multiplier coupled to the first multiplier for multiplying the first output signal by a signal having substantially the same offset frequency (.DELTA.f) to produce a second output signal having the desired signal shifted to baseband frequency and the undesired DC offset shifted in frequency to the offset frequency .DELTA.f. In addition, a filter coupled to the second multiplier filters the output signal to remove the undesired DC offset while leaving the desired signal, now located at baseband frequency, intact.
    • 一种使用频移和滤波技术的方法和装置,用于将具有中频的期望信号的输入信号和不期望的DC偏移转换成消除不期望的DC偏移的基带频率信号。 该装置包括第一乘法器,用于将输入信号乘以具有基本相同的中频加偏移频率(DELTA f)的信号,以产生第一输出信号,其中期望的信号在频率上移动到偏移频率(DELTA f) 并且不期望的DC偏移不受影响。 该装置还包括耦合到第一乘法器的第二乘法器,用于将第一输出信号乘以具有基本相同偏移频率(DELTA f)的信号,以产生具有偏移到基带频率的期望信号的第二输出信号和不期望的DC偏移 频率偏移到偏移频率DELTA f。 此外,耦合到第二乘法器的滤波器对输出信号进行滤波以去除不期望的DC偏移,同时留下现在位于基带频率处的所需信号。