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1. 发明授权

US07129169B2 Method for controlling voiding and bridging in silicide formation 有权
标题翻译：控制硅化物形成中孔隙和桥接的方法
公开(公告)号：US07129169B2
公开(公告)日：2006-10-31
申请号：US10709534
申请日：2004-05-12
申请人： Bradley P. Jones , Christian Lavoie , Robert J. Purtell , Yun-Yu Wang , Keith Kwong Hon Wong
发明人： Bradley P. Jones , Christian Lavoie , Robert J. Purtell , Yun-Yu Wang , Keith Kwong Hon Wong
IPC分类号： H01L21/44 , H01L21/3205
CPC分类号： H01L29/665 , H01L21/28518 , H01L29/7833
摘要： A method for forming a metal silicide contact for a semiconductor device includes forming a refractory metal layer over a substrate, including active and non-active area of said substrate, and forming a cap layer over the refractory metal layer. A counter tensile layer is formed over the cap layer, wherein the counter tensile layer is selected from a material such that an opposing directional stress is created between the counter tensile layer and the cap layer, with respect to a directional stress created between the refractory metal layer and the cap layer.
摘要翻译：一种用于形成用于半导体器件的金属硅化物接触的方法包括在衬底上形成难熔金属层，该衬底包括所述衬底的有源区和非有源区，并在难熔金属层上形成覆盖层。反面拉伸层形成在覆盖层上方，其中相对抗拉层选自材料，使得在相对拉伸层和盖层之间产生相对的方向应力，相对于难熔金属之间产生的方向应力层和盖层。

2. 发明授权

US07320938B2 Method for reducing dendrite formation in nickel silicon salicide processes 失效
标题翻译：减少硅化硅化硅工艺中的枝晶形成的方法
公开(公告)号：US07320938B2
公开(公告)日：2008-01-22
申请号：US11460671
申请日：2006-07-28
申请人： Robert J. Purtell , Yun-Yu Wang , Keith Kwong Hon Wong
发明人： Robert J. Purtell , Yun-Yu Wang , Keith Kwong Hon Wong
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： A method for reducing dendrite formation in a self-aligned, silicide process for a semiconductor device includes forming a silicide metal layer over a semiconductor substrate, the semiconductor device having one or more diffusion regions, one or more isolation areas and one or more gate structures formed thereon. The concentration of metal rich portions of the metal layer is reduced through the introduction of silicon thereto, and the semiconductor device is annealed.
摘要翻译：用于减少半导体器件的自对准硅化物工艺中的枝晶形成的方法包括在半导体衬底上形成硅化物金属层，所述半导体器件具有一个或多个扩散区域，一个或多个隔离区域和一个或多个栅极结构形成在其上。金属层的富金属部分的浓度通过向其中引入硅而降低，半导体器件退火。

3. 发明授权

US07109116B1 Method for reducing dendrite formation in nickel silicon salicide processes 失效
标题翻译：减少硅化硅化硅工艺中的枝晶形成的方法
公开(公告)号：US07109116B1
公开(公告)日：2006-09-19
申请号：US11161064
申请日：2005-07-21
申请人： Robert J. Purtell , Yun-Yu Wang , Keith Kwong Hon Wong
发明人： Robert J. Purtell , Yun-Yu Wang , Keith Kwong Hon Wong
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： A method for reducing dendrite formation in a self-aligned, silicide process for a semiconductor device includes forming a silicide metal layer over a semiconductor substrate, the semiconductor device having one or more diffusion regions, one or more isolation areas and one or more gate structures formed thereon. The concentration of metal rich portions of the metal layer is reduced through the introduction of silicon thereto, and the semiconductor device is annealed.
摘要翻译：用于减少半导体器件的自对准硅化物工艺中的枝晶形成的方法包括在半导体衬底上形成硅化物金属层，所述半导体器件具有一个或多个扩散区域，一个或多个隔离区域和一个或多个栅极结构形成在其上。金属层的富金属部分的浓度通过向其中引入硅而降低，半导体器件退火。

4. 发明授权

US07659199B2 Air break for improved silicide formation with composite caps 失效
标题翻译：用复合盖改善硅化物形成的空气断裂
公开(公告)号：US07659199B2
公开(公告)日：2010-02-09
申请号：US12062592
申请日：2008-04-04
申请人： Robert J. Purtell , Keith Kwong Hon Wong
发明人： Robert J. Purtell , Keith Kwong Hon Wong
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , H01L29/665 , H01L29/7833
摘要： Disclosed is a structure and method for tuning silicide stress and, particularly, for developing a tensile silicide region on a gate conductor of an n-FET in order to optimize n-FET performance. More particularly, a first metal layer-protective cap layer-second metal layer stack is formed on an n-FET structure. However, prior to the deposition of the second metal layer, the protective layer is exposed to air. This air break step alters the adhesion between the protective cap layer and the second metal layer and thereby, effects the stress imparted upon the first metal layer during silicide formation. The result is a more tensile silicide that is optimal for n-FET performance. Additionally, the method allows such a tensile silicide region to be formed using a relatively thin first metal layer-protective cap layer-second metal layer stack, and particularly, a relatively thin second metal layer, to minimize mechanical energy build up at the junctions between the gate conductor and the sidewall spacers to avoid silicon bridging.
摘要翻译：公开了一种用于调整硅化物应力的结构和方法，特别是用于在n-FET的栅极导体上形成拉伸硅化物区域，以优化n-FET性能。更具体地，在n-FET结构上形成第一金属层保护盖层 - 第二金属层堆叠。然而，在沉积第二金属层之前，保护层暴露于空气中。这种空气破碎步骤改变了保护盖层和第二金属层之间的粘附，从而在硅化物形成期间实现施加在第一金属层上的应力。结果是对于n-FET性能最佳的更强的硅化物。此外，该方法允许使用相对较薄的第一金属层 - 保护层 - 第二金属层堆叠形成这种拉伸硅化物区域，特别是相对较薄的第二金属层，以最小化在栅极导体和侧壁间隔件，以避免硅桥接。

5. 发明授权

US07622386B2 Method for improved formation of nickel silicide contacts in semiconductor devices 失效
标题翻译：用于改善半导体器件中硅化镍触点形成的方法
公开(公告)号：US07622386B2
公开(公告)日：2009-11-24
申请号：US11567517
申请日：2006-12-06
申请人： Anita Madan , Robert J. Purtell , Keith Kwong Hon Wong , Jun-Keun Kwak
发明人： Anita Madan , Robert J. Purtell , Keith Kwong Hon Wong , Jun-Keun Kwak
IPC分类号： H01L21/44
CPC分类号： H01L21/28518
摘要： A method of forming silicide contacts for semiconductor devices includes subjecting a silicon containing semiconductor wafer to a degas treatment at an initial degas temperature of about 250 to about 400° C., transferring the semiconductor wafer from a degas chamber to a deposition chamber, depositing a nickel containing layer over the wafer following transfer of the wafer from the degas chamber to the deposition chamber, and annealing the semiconductor wafer so as to create silicide regions at portions on the wafer where nickel material is formed over silicon.
摘要翻译：形成用于半导体器件的硅化物触点的方法包括在约250至约400℃的初始脱气温度下对含硅半导体晶片进行脱气处理，将半导体晶片从脱气室转移至沉积室，将晶片从脱气室转移到沉积室之后，在晶片上方的镍含量层，以及对半导体晶片进行退火，以在晶片上形成硅材料的部分上形成硅化物区域，其中镍材料形成在硅上。

6. 发明申请

US20080220604A1 AIR BREAK FOR IMPROVED SILICIDE FORMATION WITH COMPOSITE CAPS 失效
标题翻译：用于改进硅酸盐形成与复合CAPS的空气破裂
公开(公告)号：US20080220604A1
公开(公告)日：2008-09-11
申请号：US12062592
申请日：2008-04-04
申请人： Robert J. Purtell , Keith Kwong Hon Wong
发明人： Robert J. Purtell , Keith Kwong Hon Wong
IPC分类号： H01L21/3205
CPC分类号： H01L21/28518 , H01L29/665 , H01L29/7833
摘要： Disclosed is a structure and method for tuning silicide stress and, particularly, for developing a tensile silicide region on a gate conductor of an n-FET in order to optimize n-FET performance. More particularly, a first metal layer-protective cap layer-second metal layer stack is formed on an n-FET structure. However, prior to the deposition of the second metal layer, the protective layer is exposed to air. This air break step alters the adhesion between the protective cap layer and the second metal layer and thereby, effects the stress imparted upon the first metal layer during silicide formation. The result is a more tensile silicide that is optimal for n-FET performance. Additionally, the method allows such a tensile silicide region to be formed using a relatively thin first metal layer-protective cap layer-second metal layer stack, and particularly, a relatively thin second metal layer, to minimize mechanical energy build up at the junctions between the gate conductor and the sidewall spacers to avoid silicon bridging.
摘要翻译：公开了一种用于调整硅化物应力的结构和方法，特别是用于在n-FET的栅极导体上形成拉伸硅化物区域，以优化n-FET性能。更具体地，在n-FET结构上形成第一金属层保护盖层 - 第二金属层堆叠。然而，在沉积第二金属层之前，保护层暴露于空气中。这种空气破碎步骤改变了保护盖层和第二金属层之间的粘附，从而在硅化物形成期间实现施加在第一金属层上的应力。结果是对于n-FET性能最佳的更强的硅化物。此外，该方法允许使用相对较薄的第一金属层 - 保护层 - 第二金属层堆叠形成这种拉伸硅化物区域，特别是相对较薄的第二金属层，以最小化在栅极导体和侧壁间隔件，以避免硅桥接。

7. 发明申请

US20080156265A1 METHOD AND APPARATUS FOR FORMING NICKEL SILICIDE WITH LOW DEFECT DENSITY IN FET DEVICES 有权
公开(公告)号：US20080156265A1
公开(公告)日：2008-07-03
申请号：US12047561
申请日：2008-03-13
申请人： Keith Kwong Hon Wong , Robert J. Purtell
发明人： Keith Kwong Hon Wong , Robert J. Purtell
IPC分类号： C23C16/06
CPC分类号： H01L21/28518 , C23C14/16 , C23C14/32 , C23C14/345 , H01L21/28052 , H01L21/2855 , H01L29/66507 , H01L29/78
摘要： A method and an apparatus are provided in which non-directional and directional metal (e.g. Ni) deposition steps are performed in the same process chamber. A first plasma is formed for removing material from a target; a secondary plasma for increasing ion density in the material is formed in the interior of an annular electrode (e.g. a Ni ring) connected to an RF generator. Material is deposited non-directionally on the substrate in the absence of the secondary plasma and electrical biasing of the substrate, and deposited directionally when the secondary plasma is present and the substrate is electrically biased. Nickel silicide formed from the deposited metal has a lower gate polysilicon sheet resistance and may have a lower density of pipe defects than NiSi formed from metal deposited in a solely directional process, and has a lower source/drain contact resistance than NiSi formed from metal deposited in a solely non-directional process.

8. 发明申请

US20080138985A1 METHOD FOR IMPROVED FORMATION OF NICKEL SILICIDE CONTACTS IN SEMICONDUCTOR DEVICES 失效
标题翻译：用于改善在半导体器件中形成镍硅化物接触的方法
公开(公告)号：US20080138985A1
公开(公告)日：2008-06-12
申请号：US11567517
申请日：2006-12-06
申请人： Anita Madan , Robert J. Purtell , Keith Kwong Hon Wong , Jun-Keun Kwak
发明人： Anita Madan , Robert J. Purtell , Keith Kwong Hon Wong , Jun-Keun Kwak
IPC分类号： H01L21/44
CPC分类号： H01L21/28518
摘要： A method of forming silicide contacts for semiconductor devices includes subjecting a silicon containing semiconductor wafer to a degas treatment at an initial degas temperature of about 250 to about 400° C., transferring the semiconductor wafer from a degas chamber to a deposition chamber, depositing a nickel containing layer over the wafer following transfer of the wafer from the degas chamber to the deposition chamber, and annealing the semiconductor wafer so as to create silicide regions at portions on the wafer where nickel material is formed over silicon.
摘要翻译：形成用于半导体器件的硅化物触点的方法包括在约250至约400℃的初始脱气温度下对含硅半导体晶片进行脱气处理，将半导体晶片从脱气室转移至沉积室，将晶片从脱气室转移到沉积室之后，在晶片上方的镍含量层，以及对半导体晶片进行退火，以在晶片上形成硅材料的部分上形成硅化物区域，其中镍材料形成在硅上。

9. 发明授权

US08298385B2 Method and apparatus for forming nickel silicide with low defect density in FET devices 有权
标题翻译：在FET器件中形成低缺陷密度的硅化镍的方法和装置
公开(公告)号：US08298385B2
公开(公告)日：2012-10-30
申请号：US12047561
申请日：2008-03-13
申请人： Keith Kwong Hon Wong , Robert J. Purtell
发明人： Keith Kwong Hon Wong , Robert J. Purtell
IPC分类号： C23C14/34
CPC分类号： H01L21/28518 , C23C14/16 , C23C14/32 , C23C14/345 , H01L21/28052 , H01L21/2855 , H01L29/66507 , H01L29/78
摘要： A method and an apparatus are provided in which non-directional and directional metal (e.g. Ni) deposition steps are performed in the same process chamber. A first plasma is formed for removing material from a target; a secondary plasma for increasing ion density in the material is formed in the interior of an annular electrode (e.g. a Ni ring) connected to an RF generator. Material is deposited non-directionally on the substrate in the absence of the secondary plasma and electrical biasing of the substrate, and deposited directionally when the secondary plasma is present and the substrate is electrically biased. Nickel silicide formed from the deposited metal has a lower gate polysilicon sheet resistance and may have a lower density of pipe defects than NiSi formed from metal deposited in a solely directional process, and has a lower source/drain contact resistance than NiSi formed from metal deposited in a solely non-directional process.
摘要翻译：提供了一种方法和装置，其中在相同的处理室中执行非定向和定向金属（例如Ni）沉积步骤。形成第一等离子体以从靶中去除材料; 在连接到RF发生器的环形电极（例如Ni环）的内部形成用于增加材料中的离子密度的二次等离子体。在不存在基板的二次等离子体和电偏置的情况下，材料被非定向地沉积在基板上，并且当存在二次等离子体并且基板被电偏置时定向沉积材料。由沉积金属形成的硅化镍具有较低的栅极多晶硅薄层电阻，并且可能具有比仅在单向定向工艺中沉积的金属形成的NiSi更低的管缺陷密度，并且具有比由金属沉积形成的NiSi更低的源/漏接触电阻在一个单一的无方向的过程。

10. 发明授权

US07485572B2 Method for improved formation of cobalt silicide contacts in semiconductor devices 失效
标题翻译：用于改善半导体器件中的硅化钴接触的形成的方法
公开(公告)号：US07485572B2
公开(公告)日：2009-02-03
申请号：US11534714
申请日：2006-09-25
申请人： Anita Madan , Robert J. Purtell , Keith Kwong Hon Wong
发明人： Anita Madan , Robert J. Purtell , Keith Kwong Hon Wong
IPC分类号： H01L29/45
CPC分类号： H01L21/28518
摘要： A method of forming silicide contacts for semiconductor devices includes subjecting a silicon containing semiconductor wafer to a degas treatment at a temperature of about 400° C., transferring the semiconductor wafer from a degas chamber to a deposition chamber, depositing a cobalt layer over the wafer at a point in time when the semiconductor wafer has cooled to temperature range of about 275-300° C., depositing a cap layer over the cobalt layer, and annealing the semiconductor wafer so as to create silicide contacts at portions on the wafer where cobalt is formed over silicon.
摘要翻译：一种形成用于半导体器件的硅化物接触的方法包括在约400℃的温度下对含硅半导体晶片进行脱气处理，将半导体晶片从脱气室转移到沉积室，在晶片上沉积钴层在半导体晶片已经冷却到约275-300℃的温度范围的时间点，在钴层上沉积覆盖层，并对半导体晶片进行退火，以在晶片上的部分形成硅化物接触，其中钴在硅上形成。

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