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1. 发明授权

US06764006B1 Apparatus and/or method to reduce bias current for MR reader during read only operation 有权
标题翻译：在只读操作期间减少MR读取器的偏置电流的装置和/或方法
公开(公告)号：US06764006B1
公开(公告)日：2004-07-20
申请号：US10208406
申请日：2002-07-30
申请人： Robert G. Brocko , Keith G. Boyer , James C. Cates , Larry D. Blanchard
发明人： Robert G. Brocko , Keith G. Boyer , James C. Cates , Larry D. Blanchard
IPC分类号： G06K708
CPC分类号： G11B5/00813 , G11B2005/0013 , G11B2005/0016 , G11B2005/0018
摘要： An apparatus includes a tape read head bias signal control circuit configured to present to a tape read head a first amplitude bias signal in response to at least a first control signal and a second amplitude bias signal in response to at least a second control signal, wherein the second amplitude is lower than the first amplitude. The read head, thereby, may have a reduced operating temperature.
摘要翻译：一种装置包括：带读取头偏置信号控制电路，配置为响应于至少第二控制信号，响应于至少第一控制信号和第二幅度偏置信号向磁带读取头呈现第一幅度偏置信号，其中第二幅度低于第一幅度。因此读头可能具有降低的工作温度。

2. 发明申请

US20090019335A1 AUXILIARY PATH ITERATIVE DECODING 有权
标题翻译：辅助路径迭代解码
公开(公告)号：US20090019335A1
公开(公告)日：2009-01-15
申请号：US11775748
申请日：2007-07-10
申请人： Keith G. Boyer , Jin Lu , Mark Hennecken
发明人： Keith G. Boyer , Jin Lu , Mark Hennecken
IPC分类号： H03M13/29
CPC分类号： H03M13/1105 , H03M13/47 , H03M13/6561
摘要： A parallel iterative decoding system interposed between a network interface and a block memory matrix receives encoded data and both stores the data in a First-In-First-Out (“FIFO”) memory block and processes it through a timing recovery engine. The timing recovery engine delivers to an iterative decoder synchronized data samples and detects cycle slip. The iterative decoder thereafter performs a predetermined number of iterations to decode the data. Responsive to encoded data failing to converge after the predetermined number of iterations, the encoded data is communicated from the FIFO memory to an auxiliary decoder module. The auxiliary iterative error correction code decoder performs a second predetermined number of iterations to decode the data wherein the number of iterations performed by the auxiliary iterative error correction code decoder is greater than the primary iterative error correction code decoder. Converged data from the auxiliary decoder replaces otherwise null data stored in the block matrix memory.
摘要翻译：插入在网络接口和块存储器矩阵之间的并行迭代解码系统接收编码数据，并将数据存储在先进先出（“FIFO”）存储器块中，并通过定时恢复引擎进行处理。定时恢复引擎提供迭代解码器同步数据采样并检测周期滑移。迭代解码器此后执行预定数量的迭代来解码数据。响应编码数据在预定次数的迭代之后不能收敛，编码数据从FIFO存储器传送到辅助解码器模块。辅助迭代纠错码解码器执行第二预定次数的迭代以解码其中由辅助迭代纠错码解码器执行的迭代次数大于主迭代纠错码解码器的数据。来自辅助解码器的汇聚数据替换存储在块矩阵存储器中的空数据。

3. 发明授权

US06311259B1 System and method for reading unidirectionally recorded data bidirectionally 失效
标题翻译：双向读取单向记录数据的系统和方法
公开(公告)号：US06311259B1
公开(公告)日：2001-10-30
申请号：US08777054
申请日：1996-12-30
申请人： Keith G. Boyer , Richard A. Gill , Thomas H. Gohl
发明人： Keith G. Boyer , Richard A. Gill , Thomas H. Gohl
IPC分类号： G06F926
CPC分类号： G06F7/785 , G11B20/00086 , G11B20/0021
摘要： A system and method for allowing uni-directional data to be read in the reverse direction as well as the forward direction uses a data buffer to reverse the order of data read from storage media. Data are read from the storage media in the reverse direction and stored in a data buffer. Pointers are set up to track record boundaries of the data storedin the data buffer. The data are read from the data buffer in the opposite direction from which they are stored and sent to a host in the forward direction. Cyclic redundancy checks can be performed as data are read from the storage media in the reverse direction and read from the data buffer in the forward direction.
摘要翻译：用于允许在相反方向和正向读取单向数据的系统和方法使用数据缓冲器来反转从存储介质读取的数据的顺序。数据从存储介质反方向读取并存储在数据缓冲器中。指针设置为跟踪存储在数据缓冲区中的数据的记录边界。从数据缓冲器中读取数据的方向与存储数据的方向相反，向前发送到主机。可以执行循环冗余检查，因为从反方向从存储介质读取数据，并从数据缓冲区向前读取数据。

4. 发明授权

US5533039A Fault tolerant fiber optic protocol for determining beginning of data 失效
标题翻译：用于确定数据开始的容错光纤协议
公开(公告)号：US5533039A
公开(公告)日：1996-07-02
申请号：US125337
申请日：1993-09-22
申请人： Keith G. Boyer
发明人： Keith G. Boyer
IPC分类号： G06F7/74 , G06F11/00 , H04L1/00 , G06F7/02
CPC分类号： G06F7/74 , H04L1/0083
摘要： A fault tolerant protocol for determining the beginning of data despite the presence of burst errors in a frame of transmitted data. The fault tolerant protocol of the present invention provides in the frame of transmitted data a plurality of different preamble characters, P, in a prearranged order before the beginning of data. The frame of transmitted data before the plurality of preamble characters is a plurality of identical synchronization characters, S. The protocol of the present invention detects a predetermined number, n, of sequential synchronization characters in the plurality, s, of synchronization characters. Upon detection, a synchronization signal is issued indicating acquisition of synchronization. Upon receipt of the synchronization signal, the invention detects a majority, m, of preamble characters in the plurality of preamble characters. When a majority of the preamble characters have been detected, the beginning of data is determined.
摘要翻译：尽管在发送数据的帧中存在突发错误，但是用于确定数据开始的容错协议。本发明的容错协议在发送数据的帧中以数据开始之前的预定顺序提供多个不同的前同步码字符P。在多个前导码字符之前的发送数据的帧是多个相同的同步字符S.本发明的协议检测多个同步字符的预定数量n个顺序同步字符。在检测到时，发出指示同步的获取的同步信号。在接收到同步信号时，本发明检测多个前导码字符中的前导码字符的多数，m。当检测到大多数前导码字符时，确定数据的开始。

5. 发明授权

US08413014B2 Cycle slip detection and correction 有权
标题翻译：循环滑移检测和校正
公开(公告)号：US08413014B2
公开(公告)日：2013-04-02
申请号：US12511664
申请日：2009-07-29
申请人： Jin Lu , Keith G. Boyer
发明人： Jin Lu , Keith G. Boyer
IPC分类号： G11C29/42 , G11C29/00
CPC分类号： H03M13/1102 , G11B20/18 , G11B2020/185 , G11B2220/90 , H03M13/03 , H03M13/033 , H03M13/41 , H03M13/6331 , H03M13/6343
摘要： A method of writing data to and reading data from a storage medium includes cycle slip detection and correction. An LDPC matrix includes a first area for cycle slip detection and correction. The first area satisfies a set of conditions such that a cycle slip at a particular position creates a pattern of parity check errors indicative of the position and polarity of the cycle slip. Writing user data to the storage medium includes encoding the user data with parity data according to the LDPC matrix. Reading the user data and the parity data from the storage medium includes decoding the user data and the parity data according to the LDPC matrix. Decoding includes, upon detecting a pattern of parity check errors indicative of the position and polarity of a detected cycle slip, correcting the detected cycle slip.
摘要翻译：将数据写入存储介质并从存储介质读取数据的方法包括循环滑移检测和校正。 LDPC矩阵包括用于循环滑移检测和校正的第一区域。第一区域满足一组条件，使得特定位置处的循环滑移创建指示循环滑移的位置和极性的奇偶校验错误的模式。将用户数据写入存储介质包括根据LDPC矩阵对具有奇偶校验数据的用户数据进行编码。从存储介质读取用户数据和奇偶校验数据包括根据LDPC矩阵对用户数据和奇偶校验数据进行解码。解码包括在检测到指示检测到的循环滑移的位置和极性的奇偶校验错误的模式时，校正检测到的循环滑移。

6. 发明授权

US07409622B1 System and method for reverse error correction coding 有权
标题翻译：用于反向纠错编码的系统和方法
公开(公告)号：US07409622B1
公开(公告)日：2008-08-05
申请号：US11272265
申请日：2005-11-10
申请人： Jin Lu , Keith G. Boyer
发明人： Jin Lu , Keith G. Boyer
IPC分类号： H03M13/00
CPC分类号： H03M13/31 , H03M5/145 , H03M13/1102 , H03M13/15 , H03M13/1515 , H03M13/27
摘要： A system and method for Reverse Error Correction Coding. The system includes a Constraint encoder, an Error Correction Code encoder, and a uniform interleaver. The Constraint encoder receives a source data stream and generates a first intermediate encoded data stream satisfying a first predetermined timing data constraint. The Error Correction Code encoder receives the first intermediate encoded data stream and generates a second intermediate encoded data stream having one or more Error Correction Code based elements. The uniform interleaver receives the second intermediate encoded data stream and generates a channel data stream having the one or more Error Correction Code based elements and satisfying a second predetermined timing data constraint.
摘要翻译：一种用于反向纠错编码的系统和方法。该系统包括约束编码器，纠错码编码器和统一交织器。约束编码器接收源数据流并产生满足第一预定定时数据约束的第一中间编码数据流。纠错码编码器接收第一中间编码数据流并产生具有一个或多个基于错误校正码的元件的第二中间编码数据流。均匀交织器接收第二中间编码数据流，并产生具有一个或多个基于错误纠正码的元素并满足第二预定定时数据约束的信道数据流。

7. 发明授权

US08006172B2 Auxiliary path iterative decoding 有权
标题翻译：辅助路径迭代解码
公开(公告)号：US08006172B2
公开(公告)日：2011-08-23
申请号：US11775748
申请日：2007-07-10
申请人： Keith G. Boyer , Jin Lu , Mark Hennecken
发明人： Keith G. Boyer , Jin Lu , Mark Hennecken
IPC分类号： H03M13/03 , G06F11/00
CPC分类号： H03M13/1105 , H03M13/47 , H03M13/6561
摘要： A parallel iterative decoding system interposed between a network interface and a block memory matrix receives encoded data and both stores the data in a First-In-First-Out (“FIFO”) memory block and processes it through a timing recovery engine. The timing recovery engine delivers to an iterative decoder synchronized data samples and detects cycle slip. The iterative decoder thereafter performs a predetermined number of iterations to decode the data. Responsive to encoded data failing to converge after the predetermined number of iterations, the encoded data is communicated from the FIFO memory to an auxiliary decoder module. The auxiliary iterative error correction code decoder performs a second predetermined number of iterations to decode the data wherein the number of iterations performed by the auxiliary iterative error correction code decoder is greater than the primary iterative error correction code decoder. Converged data from the auxiliary decoder replaces otherwise null data stored in the block matrix memory.
摘要翻译：插入在网络接口和块存储器矩阵之间的并行迭代解码系统接收编码数据，并将数据存储在先进先出（“FIFO”）存储器块中，并通过定时恢复引擎进行处理。定时恢复引擎提供迭代解码器同步数据采样并检测周期滑移。迭代解码器此后执行预定数量的迭代来解码数据。响应编码数据在预定次数的迭代之后不能收敛，编码数据从FIFO存储器传送到辅助解码器模块。辅助迭代纠错码解码器执行第二预定次数的迭代以解码其中由辅助迭代纠错码解码器执行的迭代次数大于主迭代纠错码解码器的数据。来自辅助解码器的汇聚数据替换存储在块矩阵存储器中的空数据。

8. 发明申请

US20110029843A1 CYCLE SLIP DETECTION AND CORRECTION 有权
标题翻译：循环滑移检测和校正
公开(公告)号：US20110029843A1
公开(公告)日：2011-02-03
申请号：US12511664
申请日：2009-07-29
申请人： Jin Lu , Keith G. Boyer
发明人： Jin Lu , Keith G. Boyer
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/1102 , G11B20/18 , G11B2020/185 , G11B2220/90 , H03M13/03 , H03M13/033 , H03M13/41 , H03M13/6331 , H03M13/6343
摘要： A method of writing data to and reading data from a storage medium includes cycle slip detection and correction. An LDPC matrix includes a first area for cycle slip detection and correction. The first area satisfies a set of conditions such that a cycle slip at a particular position creates a pattern of parity check errors indicative of the position and polarity of the cycle slip. Writing user data to the storage medium includes encoding the user data with parity data according to the LDPC matrix. Reading the user data and the parity data from the storage medium includes decoding the user data and the parity data according to the LDPC matrix. Decoding includes, upon detecting a pattern of parity check errors indicative of the position and polarity of a detected cycle slip, correcting the detected cycle slip.
摘要翻译：将数据写入存储介质并从存储介质读取数据的方法包括循环滑移检测和校正。 LDPC矩阵包括用于循环滑移检测和校正的第一区域。第一区域满足一组条件，使得特定位置处的循环滑移创建指示循环滑移的位置和极性的奇偶校验错误的模式。将用户数据写入存储介质包括根据LDPC矩阵对具有奇偶校验数据的用户数据进行编码。从存储介质读取用户数据和奇偶校验数据包括根据LDPC矩阵对用户数据和奇偶校验数据进行解码。解码包括在检测到指示检测到的循环滑移的位置和极性的奇偶校验错误的模式时，校正检测到的循环滑移。

9. 发明授权

US5410546A Apparatus and method for CRC computation over fixed length blocks containing variable length packets of data received out of order 失效
标题翻译：在包含可变长度数据包的固定长度块上进行CRC计算的装置和方法，其顺序接收
公开(公告)号：US5410546A
公开(公告)日：1995-04-25
申请号：US146531
申请日：1993-11-01
申请人： Keith G. Boyer , Kenneth R. Burns , Thomas H. Gohl , Terry R. Gottehrer , Bernie R. Marasco , Michael R. Stephens , Robert D. Thompson
发明人： Keith G. Boyer , Kenneth R. Burns , Thomas H. Gohl , Terry R. Gottehrer , Bernie R. Marasco , Michael R. Stephens , Robert D. Thompson
IPC分类号： G06F11/10 , H03M13/09
CPC分类号： H03M13/091 , G06F11/10 , G06F11/1004
摘要： The present invention discloses a method and apparatus for computing CRC codes for fixed length page buffers of user data where the user data arrives from a transmission device in variable length packets with the packet contents being out of sequential order. The received data is written to a storage device after being restored to the correct sequential order. The data packets are comprised of a header portion and a data portion. The transmission and compression methods commonly employed by the transmission device dictates that the header portion of each packet follows the data portion. The present invention computes a complete CRC code for the data stored in a page buffer in real time as the packets are received by using several registers for saving intermediate CRC codes and circuitry to combine partial CRC codes for those packet portions received out of order. Additional circuitry is provided which reorders the data packet portions received out of order back into sequential order as the data is stored in a page buffer memory in real time. Computing the CRC codes in real time permits the saving of costs associated with other approaches that significantly buffer the incoming packets to permit subsequent reordering and CRC computation. The present invention assures data integrity of data from the time it is received from the compression unit until the time it is sent to the storage device. In addition, the present inventions ability to compute the CRC codes real time maintains optimal performance of data throughput of the storage subsystem. The present invention alleviates problems relating to delaying new data packet transmissions as deferred CRC computations are performed on previous packets reordered in temporary buffer memory.
摘要翻译：本发明公开了一种用于计算用户数据的固定长度页缓冲器的CRC码的方法和装置，其中用户数据以可变长度分组从传输设备到达，分组内容不顺序。接收到的数据在恢复到正确的顺序后被写入存储设备。数据分组由报头部分和数据部分组成。通常由传输设备使用的传输和压缩方法指示每个分组的报头部分遵循数据部分。本发明通过使用多个用于保存中间CRC码的寄存器和电路来组合部分接收到的CRC码，从而实时地计算存储在页缓冲器中的数据的完整CRC码。提供了附加电路，其中随着数据被实时地存储在页面缓冲存储器中，将按顺序接收的数据分组部分重新排列成顺序的顺序。实时计算CRC码可以节省与其他方法相关的成本，这些方法可以显着缓冲输入数据包，从而允许后续的重新排序和CRC计算。本发明确保从从压缩单元接收的时间到其被发送到存储设备的时间之前的数据的数据完整性。此外，本发明实时计算CRC码的能力保持了存储子系统的数据吞吐量的最佳性能。本发明缓和了延迟新数据分组传输的问题，因为对临时缓冲存储器中重新排序的先前分组执行延迟CRC计算。

10. 发明授权

US08643974B1 Dynamic reduction of tape stain accumulation on tape head assembly across multiple environments 有权
标题翻译：动态减少多个环境下磁带头组件上的胶带污渍积聚
公开(公告)号：US08643974B1
公开(公告)日：2014-02-04
申请号：US13598090
申请日：2012-08-29
申请人： Charles C. Partee , Keith G. Boyer
发明人： Charles C. Partee , Keith G. Boyer
IPC分类号： G11B21/02 , G11B5/03
CPC分类号： G11B5/41 , G11B5/40
摘要： Systems and methods that sense or obtain environmental conditions of a tape drive and dynamically apply voltage biases to tape head assembly elements based on the sensed/obtained environmental conditions to reduce tape stain accumulation and prolong tape head performance. Detection of different first and second sets of environmental conditions (e.g., in relation to temperatures, humidity levels, tape movement directions, etc.) may result in respective first and second voltage bias level sets being applied to respective first and second head assembly element sets. For instance, different first and second voltage bias level sets may be applied to the same head assembly elements (e.g., the first and second head assembly element sets may be the same), or the first and second voltage bias level sets may be applied to different head assembly elements (e.g., the first and second head assembly element sets may be at least partially different).
摘要翻译：感测或获得磁带驱动器的环境条件的系统和方法，并基于所感测/获得的环境条件动态地将电压偏压施加到磁带头组件元件，以减少磁带污渍积累并延长磁头性能。检测不同的第一和第二组环境条件（例如，关于温度，湿度水平，带移动方向等）可能导致相应的第一和第二电压偏置电平集合被施加到相应的第一和第二头组件元件组。例如，可以将不同的第一和第二电压偏置电平集合施加到相同的头部组件元件（例如，第一和第二头部组件元件组可以相同），或者可以将第一和第二电压偏置电平组应用于不同的头组件元件（例如，第一和第二头组件元件组可以至少部分不同）。

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