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1. 发明申请

US20060190668A1 Computer system architecture 有权
标题翻译：计算机系统架构
公开(公告)号：US20060190668A1
公开(公告)日：2006-08-24
申请号：US11064745
申请日：2005-02-24
申请人： Giora Biran , Matthew Cushing , Robert Drehmel , Allen Gavin , Mark Kautzman , Jamie Kuesel , Ming-I Lin , David Luick , James Marcella , Mark Maxson , Eric Mejdrich , Adam Muff , Clarence Ogilvie , Charles Woodruff
发明人： Giora Biran , Matthew Cushing , Robert Drehmel , Allen Gavin , Mark Kautzman , Jamie Kuesel , Ming-I Lin , David Luick , James Marcella , Mark Maxson , Eric Mejdrich , Adam Muff , Clarence Ogilvie , Charles Woodruff
IPC分类号： G06F13/36
CPC分类号： G06F13/4059
摘要： A high speed computer processor system has a high speed interface for a graphics processor. A preferred embodiment combines a PowerPC microprocessor called the Giga-Processor Ultralite (GPUL) 110 from International Business Machines Corporation (IBM) with a high speed interface on a multi-chip module.
摘要翻译：高速计算机处理器系统具有用于图形处理器的高速接口。优选实施例将来自国际商业机器公司（IBM）的称为Giga-Processor Ultralite（GPUL）110的PowerPC微处理器与多芯片模块上的高速接口相结合。

2. 发明申请

US20060190667A1 Pipeline bit handling circuit and method for a bus bridge 失效
标题翻译：一种总线桥管道位处理电路及方法
公开(公告)号：US20060190667A1
公开(公告)日：2006-08-24
申请号：US11064744
申请日：2005-02-24
申请人： Robert Drehmel , Clarence Ogilvie , Charles Woodruff
发明人： Robert Drehmel , Clarence Ogilvie , Charles Woodruff
IPC分类号： G06F13/36
CPC分类号： G06F13/4027 , G06F12/0831
摘要： A circuit and method to provide pipeline bit handling across a bus bridge between two different buses. In a preferred embodiment, the pipeline bit handling circuit provides rule enforcement for a P-bit address modifier across a bus bridge between two different buses with different rules for the P-bit address modifier. In a bus domain where pipeline transactions are allowed if the P-Bit is asserted and are not allowed if the P-Bit is not asserted, embodiments herein allow a master bus device to ensure that all bus devices will see a P=0 command with a defined minimum spacing to any other P=0 command. The required separation for P=0 commands is maintained within the bus bridge. In the preferred embodiments, the separation between P=0 commands is maintained by immediately retrying P=0 commands rather than spacing snoop requests.
摘要翻译：一种用于在两条不同总线之间的总线桥上提供流水线位处理的电路和方法。在优选实施例中，流水线位处理电路为P位地址修改器具有不同规则的两个不同总线之间的总线桥上的P位地址修改器提供规则强制。在一个总线域中，如果P位被断言，允许流水线事务被允许，并且如果P位不被置位则不允许流水线事务，这里的实施例允许主总线设备确保所有总线设备将看到P = 0命令，与任何其他P = 0命令的定义的最小间距。在总线桥内保持P = 0命令所需的间隔。在优选实施例中，通过立即重试P = 0命令而不是间隔窥探请求来保持P = 0命令之间的间隔。

3. 发明申请

US20060190659A1 Computer system bus bridge 失效
标题翻译：计算机系统总线桥
公开(公告)号：US20060190659A1
公开(公告)日：2006-08-24
申请号：US11064568
申请日：2005-02-24
申请人： Giora Biran , Robert Drehmel , Robert Horton , Mark Kautzman , Jamie Kuesel , Ming-i Lin , Eric Mejdrich , Clarence Ogilvie , Charles Woodruff
发明人： Giora Biran , Robert Drehmel , Robert Horton , Mark Kautzman , Jamie Kuesel , Ming-i Lin , Eric Mejdrich , Clarence Ogilvie , Charles Woodruff
IPC分类号： G06F13/36
CPC分类号： G06F13/4059 , G06F12/0831
摘要： A bus bridge between a high speed computer processor bus and a high speed output bus. The preferred embodiment is a bus bridge between a GPUL bus for a GPUL PowerPC microprocessor from International Business Machines Corporation (IBM) and an output high speed interface (MPI). Another preferred embodiment is a bus bridge in a bus transceiver on a multi-chip module.
摘要翻译：高速计算机总线与高速输出总线之间的总线桥。优选实施例是用于来自国际商业机器公司（IBM）的GPUL PowerPC微处理器的GPUL总线与输出高速接口（MPI）之间的总线桥。另一个优选实施例是多芯片模块上的总线收发器中的总线桥。

4. 发明申请

US20060190662A1 Transaction flow control mechanism for a bus bridge 有权
标题翻译：总线桥的交易流控制机制
公开(公告)号：US20060190662A1
公开(公告)日：2006-08-24
申请号：US11064722
申请日：2005-02-24
申请人： Clarence Ogilvie , Charles Woodruff
发明人： Clarence Ogilvie , Charles Woodruff
IPC分类号： G06F13/36
CPC分类号： G06F13/4059 , G06F12/0831
摘要： A transaction flow control mechanism is disclosed for a bus bridge in a high speed computer system with a high speed interface for a graphics processor. A preferred embodiment provides a flow control mechanism for the bus bridge between a GPUL bus for a GPUL PowerPC microprocessor from International Business Machines Corporation (IBM) and a high speed interface. A preferred embodiment of the invention is a bus transceiver on a multi-chip module.
摘要翻译：公开了一种用于具有用于图形处理器的高速接口的高速计算机系统中的总线桥的事务流控制机制。优选实施例提供了用于来自国际商业机器公司（IBM）的GPUL PowerPC微处理器的GPUL总线与高速接口之间的总线桥的流量控制机制。本发明的优选实施例是多芯片模块上的总线收发器。

5. 发明申请

US20060190660A1 Data ordering translation between linear and interleaved domains at a bus interface 失效
标题翻译：总线接口上的线性和交织域之间的数据排序转换
公开(公告)号：US20060190660A1
公开(公告)日：2006-08-24
申请号：US11064569
申请日：2005-02-24
申请人： Robert Horton , Clarence Ogilvie , Charles Woodruff
发明人： Robert Horton , Clarence Ogilvie , Charles Woodruff
IPC分类号： G06F13/36
CPC分类号： G06F13/4013
摘要： A bus bridge for coupling between a first bus and a second includes: at least one data buffer; data load logic and data unload logic. The data load logic places received data in the at least one data buffer, wherein the data is received at the bus bridge from across the first bus in a first data ordering. The data unload logic automatically translates the received data from the first data ordering to a second data ordering during unloading of the data from the at least one data buffer for transfer across the second bus, wherein the first data ordering and the second data ordering are each a different one of a linear data ordering and an interleaved data ordering.
摘要翻译：用于在第一总线和第二总线之间耦合的总线桥包括：至少一个数据缓冲器; 数据加载逻辑和数据卸载逻辑。数据加载逻辑将接收到的数据放置在至少一个数据缓冲器中，其中数据在总线桥接处以第一数据顺序跨越第一总线接收。在卸载来自至少一个数据缓冲器的数据的第一数据排序期间，数据卸载逻辑自动将所接收的数据从第一数据排序转换为第二数据排序，其中第一数据排序和第二数据排序分别为线性数据排序和交织数据排序中的不同之一。

6. 发明申请

US20060190651A1 Method and system for ordering requests at a bus interface 失效
标题翻译：用于在总线接口上排序请求的方法和系统
公开(公告)号：US20060190651A1
公开(公告)日：2006-08-24
申请号：US11064728
申请日：2005-02-24
申请人： Clarence Ogilvie , Charles Woodruff
发明人： Clarence Ogilvie , Charles Woodruff
IPC分类号： G06F13/22
CPC分类号： G06F13/362
摘要： A bus bridge for coupling between a first bus and a second bus includes: multiple ticket registers; a ticket dispenser counter; and a ticket call counter. The ticket dispenser counter dispenses a ticket value to a request received at the bridge from the first bus for access to the second bus. This ticket value is held in one ticket register of the multiple ticket registers. The ticket call counter provides ticket call values, and the request is granted access to the second bus when a current ticket call value equals the ticket value dispensed to the request. While the request waits for access to the second bus, the bus bridge can perform work on the request. When request coherency is maintained employing snooping, ticket values assigned to a plurality of requests maintain a snoop response ordering of the requests for access to the second bus.
摘要翻译：用于在第一总线和第二总线之间耦合的总线桥包括：多个机票寄存器; 售票柜台和一个门票柜台。售票机计数器从第一总线接收到在桥接处接收到的请求的票价值分配用于访问第二总线。该票值保存在多张票据登记册的一张票据登记册中。票券呼叫计数器提供票券呼叫值，并且当当前票券呼叫值等于分配给该请求的票值时，该请求被授权访问第二总线。当请求等待访问第二总线时，总线桥可以根据请求执行工作。当采用窥探保持请求一致性时，分配给多个请求的票值维持对访问第二总线的请求的窥探响应排序。

7. 发明申请

US20060190661A1 Method and system for controlling forwarding or terminating of a request at a bus interface based on buffer abvailability 失效
标题翻译：用于基于缓冲器可用性在总线接口处控制转发或终止请求的方法和系统
公开(公告)号：US20060190661A1
公开(公告)日：2006-08-24
申请号：US11064570
申请日：2005-02-24
申请人： Clarence Ogilvie , Charles Woodruff
发明人： Clarence Ogilvie , Charles Woodruff
IPC分类号： G06F13/36
CPC分类号： G06F13/4031 , G06F12/0831
摘要： A bus bridge for coupling between a first bus and a second bus includes: a number of data buffers for a particular request type; a counter for monitoring a number of requests of the particular type received at the bus bridge from the first bus for access to the second bus; and override logic. Each request of the particular type requires one data buffer of the number of data buffers for the particular request type. The override logic determines when the monitored number of requests of the particular type exceeds the number of data buffers for the particular request type at the bus bridge, and responsive thereto, initiates a request termination signal at the bus bridge to terminate a received request of the particular type. When request coherency is maintained employing snooping, the request termination signal is a retry snoop response signal output from the bus bridge.
摘要翻译：用于在第一总线和第二总线之间耦合的总线桥包括：用于特定请求类型的多个数据缓冲器; 一个计数器，用于监视从第一总线在总线桥接收到的特定类型的多个请求以访问第二总线; 并覆盖逻辑。特定类型的每个请求需要用于特定请求类型的数据缓冲器数量的一个数据缓冲器。覆盖逻辑确定何时监视的特定类型的请求数量超过了总线桥上特定请求类型的数据缓冲器的数量，并响应于此，在总线桥上发起请求终止信号以终止接收到的请求特定类型。当采用窥探保持请求一致性时，请求终止信号是从总线桥输出的重试监听响应信号。

8. 发明申请

US20060190655A1 Apparatus and method for transaction tag mapping between bus domains 审中-公开
标题翻译：总线域之间交易标签映射的装置和方法
公开(公告)号：US20060190655A1
公开(公告)日：2006-08-24
申请号：US11064567
申请日：2005-02-24
申请人： Mark Kautzman , Clarence Ogilvie , Charles Woodruff
发明人： Mark Kautzman , Clarence Ogilvie , Charles Woodruff
IPC分类号： G06F13/36
CPC分类号： G06F13/4027
摘要： An apparatus and method to provide tag mapping between bus domains across a bus bridge. The preferred embodiments provide a simple tag mapping design while maintaining unique IDs for all outstanding transactions for an overall increase in computer system performance. The preferred embodiment is a bus bridge between a GPUL bus for a GPUL PowerPC microprocessor from International Business Machines Corporation (IBM) and an output high speed interface (MPI bus). In preferred embodiments, the transaction mapping logic ensures that transactions generated by any logical unit (CPU) appear to originate from a single logical unit.
摘要翻译：一种通过总线桥提供总线域之间的标签映射的装置和方法。优选实施例提供简单的标签映射设计，同时为所有未完成的事务维护唯一的ID，以便计算机系统性能的总体增加。优选实施例是用于来自国际商业机器公司（IBM）的GPUL PowerPC微处理器的GPUL总线与输出高速接口（MPI总线）之间的总线桥。在优选实施例中，事务映射逻辑确保由任何逻辑单元（CPU）生成的事务似乎源于单个逻辑单元。

9. 发明授权

US06347856B1 Test pattern implementation for ink-jet printhead alignment 失效
公开(公告)号：US06347856B1
公开(公告)日：2002-02-19
申请号：US09263962
申请日：1999-03-05
申请人： Dan Arquilevich , John A Underwood , Braulio Soto , Charles Woodruff
发明人： Dan Arquilevich , John A Underwood , Braulio Soto , Charles Woodruff
IPC分类号： B41J201
CPC分类号： B41J29/393 , B41J2/2135 , B41J19/142
摘要： A method and means for automatic alignment of ink-jet printheads includes fitting measuring constructs to actual print data acquired form a print made using a given, predetermined, test pattern data set. Specific test patterns for use in automated alignment of ink-jet printheads are suited to providing a variety of printhead alignment information in a compact format. The test pattern data set incorporates techniques for avoiding carriage-induced dynamic errors during automated alignment of ink-jet printheads.

10. 发明授权

US06234602B1 Automated ink-jet printhead alignment system 有权
标题翻译：自动喷墨打印头对准系统
公开(公告)号：US06234602B1
公开(公告)日：2001-05-22
申请号：US09263594
申请日：1999-03-05
申请人： Braulio Soto , Charles Woodruff , Dan Arquilevich , John A Underwood , Rick M Tanaka , Brent A Geske
发明人： Braulio Soto , Charles Woodruff , Dan Arquilevich , John A Underwood , Rick M Tanaka , Brent A Geske
IPC分类号： B41J201
CPC分类号： B41J2/2135 , B41J29/393
摘要： A method and means for automatic alignment of ink-jet printheads includes fitting measuring constructs to actual print data acquired form a print made using a given, predetermined, test pattern data set. Specific test patterns for use in automated alignment of ink-jet printheads are suited to providing a variety of printhead alignment information in a compact format. The test pattern data set incorporates techniques for avoiding carriage-induced dynamic errors during automated alignment of ink-jet printheads.
摘要翻译：用于喷墨打印头的自动对准的方法和装置包括将测量结构拟合为从使用给定的预定的测试图案数据集所做的打印获得的实际打印数据。用于喷墨打印头的自动对准的特定测试图适用于以紧凑格式提供各种打印头对准信息。测试图案数据集包括用于在喷墨打印头的自动对准期间避免托架引起的动态误差的技术。

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