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1. 发明授权

US07728753B2 Continuous synchronization for multiple ADCs 有权
标题翻译：连续同步多个ADC
公开(公告)号：US07728753B2
公开(公告)日：2010-06-01
申请号：US12250437
申请日：2008-10-13
申请人： Robert Callaghan Taft , Heinz Werker , Pier Francese , David Barkin
发明人： Robert Callaghan Taft , Heinz Werker , Pier Francese , David Barkin
IPC分类号： H03M1/34
CPC分类号： H03M1/0624 , H03M1/123 , H03M1/1245
摘要： A system, apparatus and method for continuous synchronization of multiple ADC circuits is described. The ADC circuits can be arranged in a master-slave configuration within the system so that the converter clock is subdivided into slower speeds for the data output clock or for the control of de-multiplexing the outputs onto a wider bus, while maintaining ADC-to-ADC synchronization resilient to perturbations from noise and other upset sources. The configuration of the ADCs in the master-slave configuration can be varied according to overall system requirements in any one of a sequential configuration, a parallel configuration or a tree type of configuration, as well as others. Digital and/or analog timing adjustments can be made to each of the ADC circuits. The master clocking signals can be generated by a master clock generator circuit, which is either internally implemented in an ADC circuit, or externally implemented as a separate master clock generator circuit.
摘要翻译：描述了用于多个ADC电路的连续同步的系统，装置和方法。 ADC电路可以被布置在系统内的主从配置中，使得转换器时钟被细分为数据输出时钟的较慢速度或用于控制将输出解复用到更宽的总线上，同时保持ADC到 -ADC同步对噪声和其他扰乱源的扰动具有弹性。主从配置中的ADC的配置可以根据顺序配置，并行配置或树型配置中的任何一个的总体系统要求以及其他配置而变化。可以对每个ADC电路进行数字和/或模拟定时调整。主时钟信号可以由主时钟发生器电路产生，该主时钟发生器电路在内部实现在ADC电路中，或外部实现为单独的主时钟发生器电路。

2. 发明申请

US20100090876A1 CONTINUOUS SYNCHRONIZATION FOR MULTIPLE ADCS 有权
标题翻译：多个ADCS连续同步
公开(公告)号：US20100090876A1
公开(公告)日：2010-04-15
申请号：US12250437
申请日：2008-10-13
申请人： Robert Callaghan Taft , Heinz Werker , Pier Francese , David Brian Barkin
发明人： Robert Callaghan Taft , Heinz Werker , Pier Francese , David Brian Barkin
IPC分类号： H03M1/50
CPC分类号： H03M1/0624 , H03M1/123 , H03M1/1245
摘要： A system, apparatus and method for continuous synchronization of multiple ADC circuits is described. The ADC circuits can be arranged in a master-slave configuration within the system so that the converter clock is subdivided into slower speeds for the data output clock or for the control of de-multiplexing the outputs onto a wider bus, while maintaining ADC-to-ADC synchronization resilient to perturbations from noise and other upset sources. The configuration of the ADCs in the master-slave configuration can be varied according to overall system requirements in any one of a sequential configuration, a parallel configuration or a tree type of configuration, as well as others. Digital and/or analog timing adjustments can be made to each of the ADC circuits. The master clocking signals can be generated by a master clock generator circuit, which is either internally implemented in an ADC circuit, or externally implemented as a separate master clock generator circuit.
摘要翻译：描述了用于多个ADC电路的连续同步的系统，装置和方法。 ADC电路可以被布置在系统内的主从配置中，使得转换器时钟被细分为数据输出时钟的较慢速度或用于控制将输出解复用到更宽的总线上，同时保持ADC到 -ADC同步对噪声和其他扰乱源的扰动具有弹性。主从配置中的ADC的配置可以根据顺序配置，并行配置或树型配置中的任何一个的总体系统要求以及其他配置而变化。可以对每个ADC电路进行数字和/或模拟定时调整。主时钟信号可以由主时钟发生器电路产生，该主时钟发生器电路在内部实现在ADC电路中，或外部实现为单独的主时钟发生器电路。

3. 发明申请

US20100201559A1 Continuous synchronization for multiple ADCs 有权
公开(公告)号：US20100201559A1
公开(公告)日：2010-08-12
申请号：US12798969
申请日：2010-04-15
申请人： Robert Callaghan Taft , Heinz Werker , Pier Francese , David Brian Barkin
发明人： Robert Callaghan Taft , Heinz Werker , Pier Francese , David Brian Barkin
IPC分类号： H03M1/12
CPC分类号： H03M1/0624 , H03M1/123 , H03M1/1245
摘要： A system, apparatus and method for continuous synchronization of multiple ADC circuits is described. The ADC circuits can be arranged in a master-slave configuration within the system so that the converter clock is subdivided into slower speeds for the data output clock or for the control of de-multiplexing the outputs onto a wider bus, while maintaining ADC-to-ADC synchronization resilient to perturbations from noise and other upset sources. The configuration of the ADCs in the master-slave configuration can be varied according to overall system requirements in any one of a sequential configuration, a parallel configuration or a tree type of configuration, as well as others. Digital and/or analog timing adjustments can be made to each of the ADC circuits. The master clocking signals can be generated by a master clock generator circuit, which is either internally implemented in an ADC circuit, or externally implemented as a separate master clock generator circuit.

4. 发明授权

US07948423B2 Continuous synchronization for multiple ADCs 有权
标题翻译：连续同步多个ADC
公开(公告)号：US07948423B2
公开(公告)日：2011-05-24
申请号：US12798969
申请日：2010-04-15
申请人： Robert Callaghan Taft , Heinz Werker , Pier Francese , David Brian Barkin
发明人： Robert Callaghan Taft , Heinz Werker , Pier Francese , David Brian Barkin
IPC分类号： H03M1/12
CPC分类号： H03M1/0624 , H03M1/123 , H03M1/1245
摘要： A system, apparatus and method for continuous synchronization of multiple ADC circuits is described. The ADC circuits can be arranged in a master-slave configuration within the system so that the converter clock is subdivided into slower speeds for the data output clock or for the control of de-multiplexing the outputs onto a wider bus, while maintaining ADC-to-ADC synchronization resilient to perturbations from noise and other upset sources. The configuration of the ADCs in the master-slave configuration can be varied according to overall system requirements in any one of a sequential configuration, a parallel configuration or a tree type of configuration, as well as others. Digital and/or analog timing adjustments can be made to each of the ADC circuits. The master clocking signals can be generated by a master clock generator circuit, which is either internally implemented in an ADC circuit, or externally implemented as a separate master clock generator circuit.
摘要翻译：描述了用于多个ADC电路的连续同步的系统，装置和方法。 ADC电路可以被布置在系统内的主从配置中，使得转换器时钟被细分为数据输出时钟的较慢速度或用于控制将输出解复用到更宽的总线上，同时保持ADC到 -ADC同步对噪声和其他扰乱源的扰动具有弹性。主从配置中的ADC的配置可以根据顺序配置，并行配置或树型配置中的任何一个的总体系统要求以及其他配置而变化。可以对每个ADC电路进行数字和/或模拟定时调整。主时钟信号可以由主时钟发生器电路产生，该主时钟发生器电路在内部实现在ADC电路中，或外部实现为单独的主时钟发生器电路。

5. 发明申请

US20070274425A1 SWITCHABLE PHASE LOCKED LOOP AND METHOD FOR THE OPERATION OF A SWITCHABLE PHASE LOCKED LOOP 有权
标题翻译：可切换相位锁定环路和可切换相位锁定环路的操作方法
公开(公告)号：US20070274425A1
公开(公告)日：2007-11-29
申请号：US11751871
申请日：2007-05-22
申请人： Heinz Werker
发明人： Heinz Werker
IPC分类号： H03D3/24
CPC分类号： H03L7/22 , H03L7/0814 , H03L7/087 , H03L7/091 , H03L7/10
摘要： The invention relates to a phase locked loop or “PLL” (12) and a method for the operation of a PLL (12), wherein a controllable oscillator (DCO) generates an output signal (CKout) and can be switched over between a first clock signal (CKin1 or CKin2) and a second clock signal (CKin2 or CKin1) for use as the input clock signal of the PLL (12). According to the invention, for the clock signal (CKin1 or CKin2) currently being used to generate the output signal (CKout), a phase difference between this clock signal and the output signal (CKout) is determined and used for the control of the oscillator (DCO), whereas for the clock signal (CKin2 or CKin1) currently not being used to generate the output signal (CKout), its frequency difference with respect to the output signal (CKout) is determined and stored and continuously updated and provided for the control of the oscillator (DCO) after the switch-over to this clock signal previously not being used. The PLL output signal (CKout) can thus follow more quickly any switch-over-related frequency change of the clock signal being used.
摘要翻译：本发明涉及一种锁相环或“PLL”（12）和一种用于操作PLL（12）的方法，其中可控振荡器（DCO）产生输出信号（CKout），并且可以在第一时钟信号（CKin1或CKin2）和第二时钟信号（CKin2或CKin1），用作PLL（12）的输入时钟信号。根据本发明，对于当前用于产生输出信号（CKout）的时钟信号（CKin1或CKin2），该时钟信号和输出信号（CKout）之间的相位差被确定并用于控制振荡器（DCO），而对于当前不用于产生输出信号（CKout）的时钟信号（CKin 2或CKin 1），其相对于输出信号（CKout）的频率差被确定并存储并连续更新并提供了在切换到此时钟信号之前对振荡器（DCO）的控制。因此，PLL输出信号（CKout）可以更快速地跟踪正在使用的时钟信号的任何切换相关的频率变化。

6. 发明申请

US20080013665A1 DIGITAL PHASE DETECTOR AND A METHOD FOR THE GENERATION OF A DIGITAL PHASE DETECTION SIGNAL 有权
标题翻译：数字相位检测器及数字相位检测信号的生成方法
公开(公告)号：US20080013665A1
公开(公告)日：2008-01-17
申请号：US11773810
申请日：2007-07-05
申请人： Heinz Werker , Christian Ebner
发明人： Heinz Werker , Christian Ebner
IPC分类号： H03D3/24
CPC分类号： H03L7/093 , H03L7/091
摘要： The present invention concerns a digital phase detector (PD) and also a method for digital phase detection, as can in particular be used e.g. in a so-called phase locked loop (PLL). According to the invention a digital phase detection signal (PD_OUT) is obtained, which specifies the phasing of an input clock signal (PD_IN) with reference to a higher frequency sampling clock signal (CK). In order hereby to overcome the limitation of the phase resolution as a result of a limited performance capability, in particular limited speed of the electronic components of a sampling device (14), a new kind of concept is used, in which the sampling clock signal (CK) is not immediately used for sampling (14), but is subjected beforehand to a digitally adjustable phase displacement (12). There originates an “auxiliary sampling clock signal” (CK ). The sampling (14) delivers a first, more significant digital component (OUT1 ) of the phase detection signal (PD_OUT). Based on an evaluation of this first digital component (OUT1 ) a phase displacement (12) is undertaken and a second digital component (OUT2 ) of the phase detection signal (PD_OUT) is generated. The auxiliary sampling clock signal (CK ) is here adjustable in steps, which in each case are smaller than one period of the sampling clock signal (CK).
摘要翻译：本发明涉及数字相位检测器（PD）以及数字相位检测的方法，特别是可以使用例如数字相位检测器。在所谓的锁相环（PLL）中。根据本发明，获得数字相位检测信号（PD_OUT），其指定参考较高频率采样时钟信号（CK）的输入时钟信号（PD_IN）的定相。为了克服由于性能有限，特别是采样装置（14）的电子部件的限制速度导致的相位分辨率的限制，使用了一种新的概念，其中采样时钟信号（CK）不是立即用于采样（14），而是预先进行数字可调相移（12）。有“辅助采样时钟信号”（CK <1：8>）。采样（14）提供相位检测信号（PD_OUT）的第一个更重要的数字分量（OUT 1 <9：0>）。基于该第一数字分量（OUT 1 <9：0>）的评估，执行相位位移（12），并且生成相位检测信号（PD_OUT）的第二数字分量（OUT 2 <12：0>）。辅助采样时钟信号（CK <1：8>）在这里是可调节的，在每种情况下均小于采样时钟信号（CK）的一个周期。

7. 发明申请

US20070285177A1 SWITCHABLE PHASE LOCKED LOOP AND METHOD FOR THE OPERATION OF A SWITCHABLE PHASE LOCKED LOOP 审中-公开
标题翻译：可切换相位锁定环路和可切换相位锁定环路的操作方法
公开(公告)号：US20070285177A1
公开(公告)日：2007-12-13
申请号：US11751178
申请日：2007-05-21
申请人： Heinz Werker
发明人： Heinz Werker
IPC分类号： H03L7/00
CPC分类号： H03L7/0991 , H03L7/091
摘要： The invention relates to a phase locked loop or “PLL” (12) and a method of operating a PLL (12), wherein a controllable oscillator (DCO) generates an output signal (CKout) and it is possible to switch between a first clock (CKin1 or CKin2) and a second clock (CKin2 or CKin1) for use as a PLL (12) input clock. In accordance with the invention, for the clock (CKin1 or CKin2) currently being used to generate the output signal (CKout) a phase difference is determined between this clock and a preset phase-shifted version (CK ) of the output signal (CKout) and is used to control the oscillator (DCO), whereas for the clock (CKin2 or CKin1) not currently being used to generate the output signal (CKout), the phase shift is adjusted. In this way, a phase difference between several clocks (CKin1, CKin2, CKin3) used as the input clock is effectively adjusted or else compensated before the switchover, so that any unwanted phase change in the PLL output signal resulting from the switchover can be avoided with a high degree of accuracy and hitless switching achieved.
摘要翻译：本发明涉及锁相环或“PLL”（12）和操作PLL（12）的方法，其中可控振荡器（DCO）产生输出信号（CKout），并且可以在第一时钟（CKin 1或CKin 2）和用作PLL（12）输入时钟的第二时钟（CKin 2或CKin 1）。根据本发明，对于当前用于产生输出信号（CKout）的时钟（CKin 1或CKin 2），在该时钟和预设的相移版本（CK <1：8>）之间确定相位差，的输出信号（CKout）并用于控制振荡器（DCO），而对于当前不用于生成输出信号（CKout）的时钟（CKin 2或CKin 1），调整相移。以这种方式，用作输入时钟的多个时钟（CKin 1，CKin 2，CKin 3）之间的相位差在切换之前被有效地调整或补偿，使得由切换产生的PLL输出信号中的任何不希望的相位变化可以以高精度和无缝切换实现避免。

8. 发明授权

US07586335B2 Digital phase detector and a method for the generation of a digital phase detection signal 有权
标题翻译：数字相位检测器和用于产生数字相位检测信号的方法
公开(公告)号：US07586335B2
公开(公告)日：2009-09-08
申请号：US11773810
申请日：2007-07-05
申请人： Heinz Werker , Christian Ebner
发明人： Heinz Werker , Christian Ebner
IPC分类号： G01R25/00 , H03D13/00
CPC分类号： H03L7/093 , H03L7/091
摘要： The present invention concerns a digital phase detector (PD) and also a method for digital phase detection, as can in particular be used e.g. in a so-called phase locked loop (PLL). According to the invention a digital phase detection signal (PD_OUT) is obtained, which specifies the phasing of an input clock signal (PD_IN) with reference to a higher frequency sampling clock signal (CK). In order hereby to overcome the limitation of the phase resolution as a result of a limited performance capability, in particular limited speed of the electronic components of a sampling device (14), a new kind of concept is used, in which the sampling clock signal (CK) is not immediately used for sampling (14), but is subjected beforehand to a digitally adjustable phase displacement (12). There originates an “auxiliary sampling clock signal” (CK ). The sampling (14) delivers a first, more significant digital component (OUT1 ) of the phase detection signal (PD_OUT). Based on an evaluation of this first digital component (OUT1 ) a phase displacement (12) is undertaken and a second digital component (OUT2 ) of the phase detection signal (PD_OUT) is generated. The auxiliary sampling clock signal (CK ) is here adjustable in steps, which in each case are smaller than one period of the sampling clock signal (CK).
摘要翻译：本发明涉及数字相位检测器（PD）以及数字相位检测的方法，特别是可以使用例如数字相位检测器。在所谓的锁相环（PLL）中。根据本发明，获得数字相位检测信号（PD_OUT），其指定参考较高频率采样时钟信号（CK）的输入时钟信号（PD_IN）的定相。为了克服由于性能有限，特别是采样装置（14）的电子部件的限制速度导致的相位分辨率的限制，使用了一种新的概念，其中采样时钟信号（CK）不能立即用于采样（14），而是预先进行数字可调相移（12）。有“辅助采样时钟信号”（CK <1：8>）。采样（14）提供相位检测信号（PD_OUT）的第一个更重要的数字分量（OUT1 <9：0>）。基于对该第一数字分量（OUT1 <9：0>）的评估，进行相位位移（12），并且生成相位检测信号（PD_OUT）的第二数字分量（OUT2 <12：0>）。辅助采样时钟信号（CK <1：8>）在这里是可调节的，在每种情况下均小于采样时钟信号（CK）的一个周期。

9. 发明申请

US20070285178A1 PHASE LOCKED LOOP FOR THE GENERATION OF A PLURALITY OF OUTPUT SIGNALS 审中-公开
标题翻译：用于生成大量输出信号的相位锁定环
公开(公告)号：US20070285178A1
公开(公告)日：2007-12-13
申请号：US11751905
申请日：2007-05-22
申请人： Heinz Werker
发明人： Heinz Werker
IPC分类号： H03L7/00
CPC分类号： H03L7/087 , H03L7/18
摘要： The invention concerns a phase locked loop or “PLL” (12) as well as a method for the operation of a PLL, in which a controllable oscillator (DCO) generates an output signal (CKout) of the phase locked loop, and a phase detector (PD) determines a phase difference between a clock signal (CKin) used as an input clock signal of the PLL (12), and the PLL output signal (CKout), and provides a phase detector output signal (PD_OUT) synchronising the oscillator (DCO) with the clock signal (CKin) used. Here, in order to be able to provide a plurality of PLL output signals with an adjustable relative phase difference that are synchronised with the clock signal (CKin) provision is made according to the invention that for the determination of the phase difference an adjusted phase-shifted version (CK ) of the output signal (CKout) of the PLL is generated and compared with the phase of the clock signal being used (CKin), and that the adjusted phase-shifted version (CK ) of the PLL output signal (CKout) is provided as a further PLL output signal (CK ).
摘要翻译：本发明涉及一种锁相环或“PLL”（12）以及用于操作PLL的方法，其中可控振荡器（DCO）产生锁相环的输出信号（CKout），以及相位检测器（PD）确定用作PLL（12）的输入时钟信号的时钟信号（CKin）与PLL输出信号（CKout）之间的相位差，并提供使振荡器同步的相位检测器输出信号（PD_OUT）（DCO），使用时钟信号（CKin）。这里，为了能够提供具有与时钟信号（CKin）同步的可调节的相对相位差的多个PLL输出信号，根据本发明提出了为了确定相位差，产生PLL的输出信号（CKout）的移位版本（CK <1：8>），并与正在使用的时钟信号的相位（CKin）进行比较，调整后的相移版本（CK <1：（CKout）的另一个PLL输出信号（CK <1>）提供。

10. 发明授权

US5471512A Phase-locked loop configuration 失效
标题翻译：锁相环配置
公开(公告)号：US5471512A
公开(公告)日：1995-11-28
申请号：US285399
申请日：1994-08-03
申请人： Heinz Werker
发明人： Heinz Werker
IPC分类号： H03K5/13 , H03K5/133 , H03K17/96 , H03L7/081 , H03L7/06 , H03K5/159 , G06F1/12
CPC分类号： H03K5/133 , H03L7/0812 , H03K2017/9606
摘要： A phase-locked loop configuration includes a controllable delay device having a signal path with at least one inverter having supply lines, at least one field effect transistor having a load path, and at least one capacitor connecting the load path transversely to the signal path. A phase detector receives a reference signal and receives an input signal through the delay device. A first controller is connected downstream of the phase detector for controlling the load path of the at least one field effect transistor in the delay device. At least one pair of further field-effect transistors has load paths connected into the supply lines of the at least one inverter. A second controller is connected downstream of the phase detector for controlling the load paths of the further field effect transistors.
摘要翻译：锁相环配置包括具有至少一个具有电源线的反相器的信号路径的可控延迟装置，至少一个具有负载路径的场效应晶体管和至少一个电容器，其将负载路径横向于信号路径连接。相位检测器接收参考信号并通过延迟装置接收输入信号。第一控制器连接在相位检测器的下游，用于控制延迟装置中的至少一个场效应晶体管的负载路径。至少一对另外的场效应晶体管具有连接到所述至少一个反相器的电源线中的负载路径。第二控制器连接在相位检测器的下游，用于控制另外的场效应晶体管的负载路径。

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