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1. 发明申请

US20150278068A1 INITIALIZATION TRACE OF A COMPUTING DEVICE 审中-公开
标题翻译：计算机设备的初始化跟踪
公开(公告)号：US20150278068A1
公开(公告)日：2015-10-01
申请号：US14226612
申请日：2014-03-26
申请人： Robert C. Swanson , C. Brendan Traw , Vincent J. Zimmer , Mallik Bulusu , John R. Lindsley , Mahesh S. Natu , Dimitrios Ziakas , Robert W. Cone , Madhusudhan Rangarajan , Babak Nikjou , Kirk D. Brannock , Russell J. Wunderlich , Miles F. Schwartz , Stephen S. Pawlowski
发明人： Robert C. Swanson , C. Brendan Traw , Vincent J. Zimmer , Mallik Bulusu , John R. Lindsley , Mahesh S. Natu , Dimitrios Ziakas , Robert W. Cone , Madhusudhan Rangarajan , Babak Nikjou , Kirk D. Brannock , Russell J. Wunderlich , Miles F. Schwartz , Stephen S. Pawlowski
IPC分类号： G06F11/34 , G06F9/44
CPC分类号： G06F11/3476 , G06F9/4403 , G06F9/4416 , G06F11/1417 , G06F21/575 , G06F2201/84
摘要： Platform controller, computer-readable storage media, and methods associated with initialization of a computing device. In embodiments, a platform controller may comprise a boot controller and one or more non-volatile memory modules, coupled with the boot controller. In embodiments, the one or more non-volatile memory modules may have first instructions and second instructions stored thereon. The first instructions may, when executed by a processor of a computing device hosting the platform controller, cause initialization of the computing device. The second instructions, when executed by the boot controller, may cause the boot controller to monitor at least a portion of the execution of the first instructions by the computing device and may generate a trace of the monitored portion of the execution of the first instructions. In embodiments, the trace may be stored in the one or more non-volatile memory modules. Other embodiments may be described and/or claimed.
摘要翻译：平台控制器，计算机可读存储介质以及与计算设备的初始化相关联的方法。在实施例中，平台控制器可以包括与引导控制器耦合的引导控制器和一个或多个非易失性存储器模块。在实施例中，一个或多个非易失性存储器模块可以具有存储在其上的第一指令和第二指令。当由托管平台控制器的计算设备的处理器执行时，第一指令可以引起计算设备的初始化。第二指令在由引导控制器执行时可能导致引导控制器监视计算设备执行第一指令的至少一部分，并且可以生成第一指令的执行的监视部分的跟踪。在实施例中，迹线可以存储在一个或多个非易失性存储器模块中。可以描述和/或要求保护其他实施例。

2. 发明授权

US10146657B2 Initialization trace of a computing device 有权
公开(公告)号：US10146657B2
公开(公告)日：2018-12-04
申请号：US14226612
申请日：2014-03-26
申请人： Robert C. Swanson , C. Brendan Traw , Vincent J. Zimmer , Mallik Bulusu , John R. Lindsley , Mahesh S. Natu , Dimitrios Ziakas , Robert W. Cone , Madhusudhan Rangarajan , Babak Nikjou , Kirk D. Brannock , Russell J. Wunderlich , Miles F. Schwartz , Stephen S. Pawlowski
发明人： Robert C. Swanson , C. Brendan Traw , Vincent J. Zimmer , Mallik Bulusu , John R. Lindsley , Mahesh S. Natu , Dimitrios Ziakas , Robert W. Cone , Madhusudhan Rangarajan , Babak Nikjou , Kirk D. Brannock , Russell J. Wunderlich , Miles F. Schwartz , Stephen S. Pawlowski
IPC分类号： G06F11/14 , G06F11/34 , G06F9/4401 , G06F21/57
摘要： Platform controller, computer-readable storage media, and methods associated with initialization of a computing device. In embodiments, a platform controller may comprise a boot controller and one or more non-volatile memory modules, coupled with the boot controller. In embodiments, the one or more non-volatile memory modules may have first instructions and second instructions stored thereon. The first instructions may, when executed by a processor of a computing device hosting the platform controller, cause initialization of the computing device. The second instructions, when executed by the boot controller, may cause the boot controller to monitor at least a portion of the execution of the first instructions by the computing device and may generate a trace of the monitored portion of the execution of the first instructions. In embodiments, the trace may be stored in the one or more non-volatile memory modules. Other embodiments may be described and/or claimed.

3. 发明申请

US20150052389A1 MANAGEABILITY REDUNDANCY FOR MICRO SERVER AND CLUSTERED SYSTEM-ON-A-CHIP DEPLOYMENTS 有权
标题翻译：微服务器和集群系统在线部署的可管理性冗余
公开(公告)号：US20150052389A1
公开(公告)日：2015-02-19
申请号：US14125516
申请日：2013-08-14
申请人： Robert C. Swanson , Mariusz Oriol , Janusz Jurski , Piotr Sawicki , Robert W. Cone , William J. O'Sullivan , Mariusz Stepka , Babak Nikjou , Madhusudhan Rangarajan , Pawel Szymanski , Piotr Kwidzinski , Robert Bahnsen , Mallik Bulusu
发明人： Robert C. Swanson , Mariusz Oriol , Janusz Jurski , Piotr Sawicki , Robert W. Cone , William J. O'Sullivan , Mariusz Stepka , Babak Nikjou , Madhusudhan Rangarajan , Pawel Szymanski , Piotr Kwidzinski , Robert Bahnsen , Mallik Bulusu
IPC分类号： G06F11/20
CPC分类号： G06F11/142 , G06F1/3296 , G06F9/4881 , G06F9/5027 , G06F9/5088 , G06F11/14 , G06F11/2023 , G06F11/2028 , G06F11/203 , G06F11/2033 , G06F11/2035 , G06F11/2043 , G06F2201/805 , G06F2201/85
摘要： Technologies for providing manageability redundancy for micro server and clustered System-on-a-Chip (SoC) deployments are presented. A configurable multi-processor apparatus may include multiple integrated circuit (IC) blocks where each IC block includes a task block to perform one or more assignable task functions and a management block to perform management functions with respect to the corresponding IC block. Each task block and each management block may include one or more instruction processors and corresponding memory. Each IC block may be controllable to perform a function of one or more other IC blocks. The IC blocks may communicate with each other via a management communication infrastructure that may include a communication path from each of the management blocks to each of the other management blocks. Via the management communication infrastructure, the management blocks may bridge communication paths between pairs of management blocks.
摘要翻译：介绍了为微服务器和集群系统级芯片（SoC）部署提供可管理性冗余的技术。可配置的多处理器装置可以包括多个集成电路（IC）块，其中每个IC块包括执行一个或多个可分配任务功能的任务块和用于执行相对于IC块的管理功能的管理块。每个任务块和每个管理块可以包括一个或多个指令处理器和对应的存储器。每个IC块可以是可控制的，以执行一个或多个其它IC块的功能。 IC块可以经由管理通信基础设施相互通信，管理通信基础设施可以包括从每个管理块到每个其他管理块的通信路径。通过管理通信基础设施，管理块可以跨越管理块对之间的通信路径。

4. 发明申请

US20150006962A1 MEMORY DUMP WITHOUT ERROR CONTAINMENT LOSS 审中-公开
标题翻译：内存丢失，没有错误的容量损失
公开(公告)号：US20150006962A1
公开(公告)日：2015-01-01
申请号：US13929562
申请日：2013-06-27
申请人： Robert C. Swanson , Robert W. Cone , Madhusudhan Rangarajan , Mallik Bulusu , Robert Bahnsen
发明人： Robert C. Swanson , Robert W. Cone , Madhusudhan Rangarajan , Mallik Bulusu , Robert Bahnsen
IPC分类号： G06F11/36
CPC分类号： G06F11/0778 , G06F11/0724
摘要： A viral condition is identified in a system that causes input/output operations to be restricted during the viral condition. Crash dump data is enabled to be written to a particular region of volatile memory during the viral condition. Further, extraction of the crash dump data to fixed memory is initiated during the viral condition.
摘要翻译：在病毒状况下导致输入/输出操作受到限制的系统中鉴定出病毒状况。在病毒状况期间，崩溃转储数据能够被写入易失性存储器的特定区域。此外，在病毒状况期间开始将崩溃转储数据提取到固定存储器。

5. 发明授权

US09547497B2 Sharing embedded hardware resources 有权
标题翻译：共享嵌入式硬件资源
公开(公告)号：US09547497B2
公开(公告)日：2017-01-17
申请号：US14129663
申请日：2013-09-27
申请人： Robert C. Swanson , Robert W. Cone , William J. O'Sullivan , Mariusz Oriol , Pawel Szymanski , Babak Nikjou , Madhusudhan Rangarajan , Janusz Jurski , Piotr Kwidzinski , Mariusz Stepka , Piotr Sawicki
发明人： Robert C. Swanson , Robert W. Cone , William J. O'Sullivan , Mariusz Oriol , Pawel Szymanski , Babak Nikjou , Madhusudhan Rangarajan , Janusz Jurski , Piotr Kwidzinski , Mariusz Stepka , Piotr Sawicki
IPC分类号： G06F9/44 , G06F15/78
CPC分类号： G06F9/4401 , G06F15/7807
摘要： Technologies for facilitating inter-system-on-a-chip (SoC) communication include a first SoC, a second SoC, and a dedicated manageability controller network. The first SoC includes a first main processor, a first manageability controller, and a memory dedicated to the first manageability controller and having manageability controller firmware stored thereon. The first manageability controller is different from the first main processor and to control functions of the first SoC. The second SoC is different from the first SoC and includes a second main processor and a second manageability control, which is different from the second main processor and to control functions of the second SoC. The second SoC is to access the manageability controller firmware of the memory of the first SoC over the dedicated manageability network.
摘要翻译：用于促进片上系统间（SoC）通信的技术包括第一SoC，第二SoC和专用可管理性控制器网络。第一SoC包括第一主处理器，第一可管理性控制器和专用于第一可管理性控制器的存储器上的可管理性控制器固件的存储器。第一个可管理性控制器与第一个主处理器不同，并且控制第一个SoC的功能。第二SoC与第一SoC不同，并且包括与第二主处理器不同的第二主处理器和第二可管理性控制器以及控制第二SoC的功能。第二个SoC是通过专用的可管理网络访问第一个SoC的内存的可管理性控制器固件。

6. 发明授权

US09577953B2 Determination of a suitable target for an initiator by a control plane processor 有权
标题翻译：通过控制平面处理器确定启动器的合适目标
公开(公告)号：US09577953B2
公开(公告)日：2017-02-21
申请号：US14128453
申请日：2013-09-27
申请人： Ramamurthy Krithivas , Jacek Reniecki , Daniel P. Daly , Madhusudhan Rangarajan
发明人： Ramamurthy Krithivas , Jacek Reniecki , Daniel P. Daly , Madhusudhan Rangarajan
IPC分类号： G06F15/16 , H04L12/931 , H04L29/08 , H04L29/12 , G06F9/00 , H04L12/24
CPC分类号： H04L61/2015 , G06F9/00 , H04L41/00 , H04L49/00 , H04L67/1097 , H04L67/28
摘要： A first computational device receives a response generated by a second computational device for a third computational device. A target that is suitable for use by the third computational device is determined. The response is transmitted with an address of the target to the third computational device.
摘要翻译：第一计算设备接收由第三计算设备的第二计算设备生成的响应。确定适合于第三计算装置使用的目标。将响应与目标的地址一起发送到第三计算设备。

7. 发明授权

US08214541B2 Method and system for uniquely identifying peripheral component devices 有权
标题翻译：用于唯一识别外围组件设备的方法和系统
公开(公告)号：US08214541B2
公开(公告)日：2012-07-03
申请号：US11422771
申请日：2006-06-07
申请人： Austin P. Bolen , Samer El Haj Mahmoud , Madhusudhan Rangarajan , Aravind Hariramasamy
发明人： Austin P. Bolen , Samer El Haj Mahmoud , Madhusudhan Rangarajan , Aravind Hariramasamy
IPC分类号： G06F3/00 , G06F1/26
CPC分类号： G06F9/4411
摘要： A system for identifying peripheral devices in an information handling system uses a path-based signature for each peripheral component device. A static table is included for listing the path of each peripheral device and is accessible to the Basic Input-Output System (BIOS). The BIOS is configured to identify peripheral components associated and determine a path-base device signature for each peripheral component.
摘要翻译：用于识别信息处理系统中的外围设备的系统使用每个外围组件设备的基于路径的签名。包含静态表格列出每个外围设备的路径，并且可以访问基本输入输出系统（BIOS）。 BIOS被配置为识别相关联的外围组件，并确定每个外围组件的基于路径的设备签名。

8. 发明授权

US08020165B2 Dynamic affinity mapping to reduce usage of less reliable resources 有权
标题翻译：动态亲和力映射以减少可靠资源的使用
公开(公告)号：US08020165B2
公开(公告)日：2011-09-13
申请号：US11467600
申请日：2006-08-28
申请人： Madhusudhan Rangarajan , Allen Chester Wynn
发明人： Madhusudhan Rangarajan , Allen Chester Wynn
IPC分类号： G06F9/46 , G06F13/00 , G06F11/00
CPC分类号： G06F9/5016
摘要： In an information handling system, a plurality of system resources are usable by at least one processor. An affinity structure includes elements describing the relative accessibility of the plurality of system resources to the processor. An affinity manager adjusts the affinity structure in response to a least a first one of the plurality of system resources operating outside of at least one operating parameter.
摘要翻译：在信息处理系统中，多个系统资源可由至少一个处理器使用。亲和度结构包括描述多个系统资源对处理器的相对可访问性的元素。亲和力管理器响应于在至少一个操作参数之外操作的多个系统资源中的至少第一个系统资源中的至少一个来调整亲和结构。

9. 发明申请

US20100192029A1 Systems and Methods for Logging Correctable Memory Errors 有权
标题翻译：记录可纠正内存错误的系统和方法
公开(公告)号：US20100192029A1
公开(公告)日：2010-07-29
申请号：US12361814
申请日：2009-01-29
申请人： Bi-Chong Wang , Vijay Nijhawan , Madhusudhan Rangarajan
发明人： Bi-Chong Wang , Vijay Nijhawan , Madhusudhan Rangarajan
IPC分类号： G06F11/22
CPC分类号： G06F11/2284
摘要： In accordance with certain embodiments of the present disclosure, an information handling system is provided. The information handling system may include a plurality of processors, each processor comprising multiple cores, a memory system coupled to the plurality of processors, and a controller coupled to the plurality of processors. The controller may be configured to: receive a local system management interrupt (SMI) signal regarding an error associated with at least one of the multiple cores, determine that the received local SMI signal triggers a global SMI based on a global SMI trigger rule, cause the plurality of processors to enter a global system management mode (SMM), and log the error in a shared resource shared by the plurality of processors during the global SMM.
摘要翻译：根据本公开的某些实施例，提供了一种信息处理系统。信息处理系统可以包括多个处理器，每个处理器包括多个核心，耦合到多个处理器的存储器系统以及耦合到多个处理器的控制器。控制器可以被配置为：接收关于与多个核心中的至少一个相关联的错误的本地系统管理中断（SMI）信号，确定接收到的本地SMI信号基于全局SMI触发规则触发全局SMI，导致所述多个处理器进入全局系统管理模式（SMM），并且在所述全局SMM期间将所述错误记录在由所述多个处理器共享的共享资源中。

10. 发明申请

US20090125695A1 Thermal Control of Memory Modules Using Proximity Information 有权
标题翻译：使用接近信息对内存模块进行热控制
公开(公告)号：US20090125695A1
公开(公告)日：2009-05-14
申请号：US12356259
申请日：2009-01-20
申请人： Madhusudhan Rangarajan , Allen Chester Wynn
发明人： Madhusudhan Rangarajan , Allen Chester Wynn
IPC分类号： G06F12/06
CPC分类号： G06F12/0223 , G06F1/206 , G06F12/0646
摘要： An information handling system includes a processor having access to a system memory. The system is operable to detect a thermal alert and identify an associated portion of system memory. The system may then modify memory allocation information used by an operating system to allocate system memory. When the thermal alert indicates a rising memory module temperature that exceeds a specified threshold, the modification of the memory allocation information causes the memory to appear to be more “distant” from the system processor(s) and thereby allocated less preferentially than other memory. If the temperature continues to rise beyond a higher threshold, a second modification of the memory allocation information is performed to simulate a “hot eject” of the memory module. As the memory module cools, the memory allocation information can be restored to simulate a hot add of the memory module and to restore the proximity of the memory module.
摘要翻译：信息处理系统包括具有对系统存储器的访问的处理器。该系统可操作以检测热警报并识别系统存储器的相关部分。系统然后可以修改由操作系统使用的内存分配信息来分配系统存储器。当热警报指示上升的存储器模块温度超过指定的阈值时，存储器分配信息的修改使得存储器看起来与系统处理器更“远”，从而比其他存储器更优先地分配。如果温度继续上升超过更高的阈值，则执行存储器分配信息的第二修改以模拟存储器模块的“热喷射”。当存储器模块冷却时，可以恢复存储器分配信息以模拟存储器模块的热添加并恢复存储器模块的接近。

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