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1. 发明申请

US20050240892A1 Suite of tools to design integrated circuits 失效
标题翻译：套件设计集成电路的工具
公开(公告)号：US20050240892A1
公开(公告)日：2005-10-27
申请号：US11156319
申请日：2005-06-18
申请人： Robert Broberg , Jonathan Byrn , Gary Delp , Michael Eneboe , Gary McClannahan , George Nation , Paul Reuland , Thomas Sandoval , Matthew Wingren
发明人： Robert Broberg , Jonathan Byrn , Gary Delp , Michael Eneboe , Gary McClannahan , George Nation , Paul Reuland , Thomas Sandoval , Matthew Wingren
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/505
摘要： A set of tools is provided herein that produces useful, proven, and correct integrated semiconductor chips. Having as input either a customer's requirements for a chip, or a design specification for a partially manufactured semiconductor chip, the tools generate the RTL for control plane interconnect; memory composition, test, and manufacture; embedded logic analysis, trace interconnection, and utilization of spare resources on the chip; I/O qualification, JTAG, boundary scan, and SSO analysis; testable clock generation, control, and distribution; interconnection of all of the shared logic in a testable manner from a transistor fabric and/or configurable blocks in the slice. The input customer requirements are first conditioned by RTL analysis tools to quickly implement its logic. The slice definition and the RTL shell provides the correct logic for a set of logic interfaces for the design specification to connect. The tools share a common database so that logical interactions do not require multiple entries. The designs are qualified, tested, and verified by other tools. The tools further optimize the placement and timing of the blocks on the chip with respect to each other and with respect to placement on a board. The suite may be run as batch processes or can be driven interactively through a common graphical user interface. The tools also have an iterative mode and a global mode. In the iterative mode, one or more of the selected tools can generate the blocks or modify a design incrementally and then look at the consequences of the addition, or change. In the global mode, the semiconductor product is designed all at once in a batch process as above and then optimized altogether. This suite of generation tools generates design views including a qualified netlist for a foundry to manufacture.
摘要翻译：本文提供了一组工具，其产生有用的，经过验证的和正确的集成半导体芯片。输入客户对芯片的要求或部分制造的半导体芯片的设计规范，这些工具产生用于控制平面互连的RTL; 记忆组成，测试和制造; 嵌入式逻辑分析，跟踪互连和芯片上备用资源的利用; I / O资格，JTAG，边界扫描和SSO分析; 可测时钟生成，控制和分配; 以可测试的方式从晶体管结构和/或片中的可配置块互连所有共享逻辑。输入客户要求首先由RTL分析工具进行调节，以快速实现其逻辑。切片定义和RTL外壳为设计规范要连接的一组逻辑接口提供正确的逻辑。这些工具共享一个公共数据库，以便逻辑交互不需要多个条目。这些设计经过其他工具的合格，测试和验证。这些工具进一步优化了芯片上的块相对于彼此以及关于板上的放置的布局和定时。该套件可以作为批处理进行运行，也可以通过通用图形用户界面进行交互式驱动。这些工具也具有迭代模式和全局模式。在迭代模式中，一个或多个所选择的工具可以生成块或逐渐修改设计，然后查看添加或更改的后果。在全球模式下，半导体产品在上述批量处理中一次性设计，然后完全优化。这套生成工具生成设计视图，包括用于制造铸造的合格网表。

2. 发明申请

US20060055441A1 Method and apparatus for calibrating a delay line 有权
标题翻译：用于校准延迟线的方法和装置
公开(公告)号：US20060055441A1
公开(公告)日：2006-03-16
申请号：US10937911
申请日：2004-09-10
申请人： Gary McClannahan , Daniel Wetzel , Gary Lippert
发明人： Gary McClannahan , Daniel Wetzel , Gary Lippert
IPC分类号： H03L7/06
CPC分类号： H03L7/0995 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C11/4076 , H03L7/0805 , H03L7/085
摘要： A delay line calibration circuit and method are provided in which a programmable master delay line drives a delay clock and has a propagation delay that is a function of a delay setting. A delay counter is clocked by the delay clock and has a delay count. A reference counter is clocked by a reference clock and has a reference count. A control circuit controls the delay and reference counters, compares a representation of the delay count to a representation of the reference count and responsively generates a modified value for the delay setting to reduce a difference between the representations of delay count and the reference count.
摘要翻译：提供延迟线校准电路和方法，其中可编程主延迟线驱动延迟时钟并具有作为延迟设置的函数的传播延迟。延迟计数器由延迟时钟计时，并具有延迟计数。参考计数器由参考时钟计时，并具有引用计数。控制电路控制延迟和参考计数器，将延迟计数的表示与参考计数的表示进行比较，并且响应地生成用于延迟设置的修改值以减少延迟计数和参考计数的表示之间的差异。

3. 发明授权

US08879570B2 Systems and methods for reconfiguring a network adapter in sleep mode 有权
标题翻译：在睡眠模式下重新配置网络适配器的系统和方法
公开(公告)号：US08879570B2
公开(公告)日：2014-11-04
申请号：US12964221
申请日：2010-12-09
申请人： Venkatesh Nagapudi , Gary McClannahan , Mark Branstad , Yash Bansal , Gustavo Lau
发明人： Venkatesh Nagapudi , Gary McClannahan , Mark Branstad , Yash Bansal , Gustavo Lau
IPC分类号： H04L12/28 , G08C17/00 , H04L12/12 , H04L12/24
CPC分类号： H04L41/0803 , H04L12/12 , Y02D50/20 , Y02D50/40
摘要： A converged network adapter in sleep mode can allow a management entity to access and alter configuration of the network adapter over the network. Configuration data such as configuration parameters, firmware, and other data related to the network adapter can be stored in a memory, which can be coupled to a portion of the adapter that receives power during sleep mode. The management entity can send configuration messages to the adapter, which messages can include commands or instructions to read or write contents of the memory. The messages can include values of the configuration parameters to be altered, firmware code, etc. The management entity can also send configuration messages to a baseboard management controller (BMC) coupled to the adapter for message validation. The adapter and the BMC can send results of memory operations back to the management entity in response messages.
摘要翻译：在睡眠模式下的融合网络适配器可以允许管理实体通过网络来访问和改变网络适配器的配置。诸如配置参数，固件和与网络适配器有关的其他数据的配置数据可以存储在存储器中，存储器可以耦合到在睡眠模式期间接收电力的适配器的一部分。管理实体可以向适配器发送配置消息，哪些消息可以包括用于读取或写入存储器的内容的命令或指令。消息可以包括要更改的配置参数的值，固件代码等。管理实体还可以将配置消息发送到耦合到适配器的消息验证的基板管理控制器（BMC）。适配器和BMC可以将响应消息中的内存操作结果发送回管理实体。

4. 发明授权

US06536014B1 Reusable configuration tool 失效
标题翻译：可重复使用的配置工具
公开(公告)号：US06536014B1
公开(公告)日：2003-03-18
申请号：US09964300
申请日：2001-09-26
申请人： Gary McClannahan , John Emery Nordman , Scott Thomas Senst , John Shaffer , Todd Jason Youngman
发明人： Gary McClannahan , John Emery Nordman , Scott Thomas Senst , John Shaffer , Todd Jason Youngman
IPC分类号： G06F1750
CPC分类号： G06F17/5045
摘要： Method, system and signal bearing medium for configuring an integrated circuit are provided. One embodiment provides a method for configuring an integrated circuit, comprising: providing a user interface for displaying one or more abstract data elements for user selection, wherein the one or more abstract data elements represent one or more controls associated with characteristics of the integrated circuit; receiving a user selection of an abstract data element; validating associated abstract rules for the user selected abstract data element; and validating product rules for the one or more product data elements associated with the user selected abstract data element, wherein the one or more product data elements represent one or more controllable features of the integrated circuit.
摘要翻译：提供了用于配置集成电路的方法，系统和信号承载介质。一个实施例提供了一种用于配置集成电路的方法，包括：提供用于显示用于用户选择的一个或多个抽象数据元素的用户界面，其中所述一个或多个抽象数据元素表示与所述集成电路的特性相关联的一个或多个控制; 接收用户对抽象数据元素的选择; 验证用户选择的抽象数据元素的相关抽象规则; 以及验证与所述用户选择的抽象数据元素相关联的所述一个或多个产品数据元素的产品规则，其中所述一个或多个产品数据元素表示所述集成电路的一个或多个可控特征。

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