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1. 发明申请

US20060045108A1 Half RDMA and half FIFO operations 失效
标题翻译：半RDMA和半FIFO操作
公开(公告)号：US20060045108A1
公开(公告)日：2006-03-02
申请号：US11017406
申请日：2004-12-20
申请人： Robert Blackmore , Fu Chang , Piyush Chaudhary , Kevin Gildea , Jason Goscinski , Rama Govindaraju , Donald Grice , Leonard Helmer , Patricia Heywood , Peter Hochschild , John Houston , Chulho Kim , Steven Martin
发明人： Robert Blackmore , Fu Chang , Piyush Chaudhary , Kevin Gildea , Jason Goscinski , Rama Govindaraju , Donald Grice , Leonard Helmer , Patricia Heywood , Peter Hochschild , John Houston , Chulho Kim , Steven Martin
IPC分类号： H04L12/56
CPC分类号： H04L67/1097
摘要： In a multinode data processing system in which nodes exchange information over a network or through a switch, a structure and mechanism is provided within the realm of Remote Direct Memory Access (RDMA) operations in which DMA operations are present on one side of the transfer but not the other. On the side in which the transfer is not carried out in DMA fashion, transfer processing is carried out under program control; this is in contrast to the transfer on the DMA side which is characteristically carried out in hardware. Usage of these combination processes is useful in programming situations where RDMA is carried out to or from contiguous locations in memory on one side and where memory locations on the other side is noncontiguous. This split mode of transfer is provided both for read and for write operations.
摘要翻译：在其中节点通过网络或通过交换机交换信息的多节点数据处理系统中，在远程直接存储器访问（RDMA）操作的领域内提供了结构和机制，其中DMA操作存在于传输的一侧，但是不是其他的在DMA方式不进行传输的一方，传送处理在程序控制下进行; 这与在硬件上进行特征性的DMA侧的传输相反。这些组合过程的使用对于在一侧执行RDMA到存储器中的连续位置并且另一侧上的存储器位置不连续地执行RDMA的编程情况是有用的。这种分离传输模式为读取和写入操作都提供。

2. 发明申请

US20060045005A1 Failover mechanisms in RDMA operations 失效
标题翻译： RDMA操作中的故障切换机制
公开(公告)号：US20060045005A1
公开(公告)日：2006-03-02
申请号：US11017574
申请日：2004-12-20
申请人： Robert Blackmore , Fu Chang , Piyush Chaudhary , Jason Goscinski , Rama Govindaraju , Leonard Helmer , Peter Hochschild , John Houston , Steven Martin , Donald Grice
发明人： Robert Blackmore , Fu Chang , Piyush Chaudhary , Jason Goscinski , Rama Govindaraju , Leonard Helmer , Peter Hochschild , John Houston , Steven Martin , Donald Grice
IPC分类号： H04J1/16
CPC分类号： H04L1/0079 , G06F11/1443 , H04L1/1809 , H04L2001/0097
摘要： In remote direct memory access transfers in a multinode data processing system in which the nodes communicate with one another through communication adapters coupled to a switch or network, failures in the nodes or in the communication adapters can produce the phenomenon known as trickle traffic, which is data that has been received from the switch or from the network that is stale but which may have all the signatures of a valid packet data. The present invention addresses the trickle traffic problem in two situations: node failure and adapter failure. In the node failure situation randomly generated keys are used to reestablish connections to the adapter while providing a mechanism for the recognition of stale packets. In the adapter failure situation, a round robin context allocation approach is used with adapter state contexts being provided with state information which helps to identify stale packets. In another approach to handling the adapter failure situation counts are assigned which provide an adapter failure number to the node which will not match a corresponding number in a context field in the adapter, thus enabling the identification of stale packets.
摘要翻译：在多节点数据处理系统中的远程直接存储器访问传输中，其中节点通过耦合到交换机或网络的通信适配器彼此通信，节点或通信适配器中的故障可能产生称为流量流量的现象，已经从交换机接收到的数据或者来自网络的数据已经过时，但是可能具有有效分组数据的所有签名。本发明解决了两种情况下的流量流量问题：节点故障和适配器故障。在节点故障情况下，随机生成的密钥用于重新建立与适配器的连接，同时提供用于识别过时数据包的机制。在适配器故障情况下，使用循环上下文分配方法，适配器状态上下文被提供有状态信息，其有助于识别过时的分组。在处理适配器故障情况的另一种方法中，分配了向适配器上下文字段中不匹配相应号码的节点提供适配器故障号，从而能够识别过时的数据包。

3. 发明申请

US20060075067A1 Remote direct memory access with striping over an unreliable datagram transport 审中-公开
标题翻译：远程直接存储器访问，具有条带化不可靠的数据报传输
公开(公告)号：US20060075067A1
公开(公告)日：2006-04-06
申请号：US11017359
申请日：2004-12-20
申请人： Robert Blackmore , Piyush Chaudhary , Jason Goscinski , Rama Govindaraju , Donald Grice , Peter Hochschild , John Houston , Chulho Kim , Steven Martin , Rajeev Sivaram , Hanhong Xue
发明人： Robert Blackmore , Piyush Chaudhary , Jason Goscinski , Rama Govindaraju , Donald Grice , Peter Hochschild , John Houston , Chulho Kim , Steven Martin , Rajeev Sivaram , Hanhong Xue
IPC分类号： G06F15/16
CPC分类号： H04L69/16 , G06F12/1081 , H04L69/166
摘要： In a multinode data processing system in which nodes exchange information over a network or through a switch, a structure and mechanism are provided which enables data packets to be sent and received in any order. Normally, if in-order transmission and receipt are required, then transmission over a single path is essential to insure proper reassembly. However, the present mechanism avoids this necessity and permits Remote Direct Memory Access (RDMA) operations to be carried out simultaneously over multiple paths. This provides a data striping mode of operation in which data transfers can be carried out much faster since packets of single or multiple RDMA messages can be portioned and transferred over several paths simultaneously, thus providing the ability to utilize the full system bandwidth that is available.
摘要翻译：在节点通过网络交换信息或通过交换机交换信息的多节点数据处理系统中，提供了能够以任何顺序发送和接收数据分组的结构和机制。通常，如果需要按顺序传输和接收，则通过单个路径的传输对于确保适当的重新组装是至关重要的。然而，本机制避免了这种必要性，并且允许在多个路径上同时执行远程直接存储器访问（RDMA）操作。这提供了数据条带化操作模式，其中数据传输可以执行得更快，因为单个或多个RDMA消息的分组可以同时分配和传输多个路径，从而提供利用可用的全部系统带宽的能力。

4. 发明申请

US20060059282A1 Snapshot interface operations 失效
公开(公告)号：US20060059282A1
公开(公告)日：2006-03-16
申请号：US11017332
申请日：2004-12-20
申请人： Piyush Chaudhary , Jason Goscinski , Rama Govindaraju , Leonard Helmer , Peter Hochschild , Deryck Hong , John Houston , Jang-Soo Lee , Steven Martin , Yuqing Zhu
发明人： Piyush Chaudhary , Jason Goscinski , Rama Govindaraju , Leonard Helmer , Peter Hochschild , Deryck Hong , John Houston , Jang-Soo Lee , Steven Martin , Yuqing Zhu
IPC分类号： G06F13/00
CPC分类号： H04L67/1097
摘要： In a multinode data processing system in which the nodes communicate with one another via communication adapters over a network or switch, the adapters are provided with a dual register mechanism for tracking microcode task status. Upon the issuance of a disruptive command that requires attention from one of the nodes, the task status maintained in one register is copied to the snapshot register. As tasks within the adapter are completed, both registers are updated, thus providing a mechanism for the nodes to determine that all tasks active at the time of the disruptive command have completed. This means that the nodes now have a mechanism for determining, as soon as possible, that all tasks that are active when a disruptive command occurs have completed, thus allowing the data processing node to perform such operations as releasing system memory that is associated with the disruptive command, thus eliminating temporal overhead that can affect performance.

5. 发明申请

US20060075057A1 Remote direct memory access system and method 审中-公开
标题翻译：远程直接内存访问系统和方法
公开(公告)号：US20060075057A1
公开(公告)日：2006-04-06
申请号：US10929943
申请日：2004-08-30
申请人： Kevin Gildea , Rama Govindaraju , Donald Grice , Peter Hochschild , Fu Chung Chang
发明人： Kevin Gildea , Rama Govindaraju , Donald Grice , Peter Hochschild , Fu Chung Chang
IPC分类号： G06F15/167
CPC分类号： H04L67/1097 , H04L67/18
摘要： A remote direct memory access (RDMA) system is provided in which data is transferred over a network by DMA between from a memory of a first node of a multi-processor system having a plurality of nodes connected by a network and a memory of a second node of the multi-processor system. The system includes a first network adapter at the first node, operable to transmit data stored in the memory of the first node to a second node in a plurality of portions in fulfillment of a DMA request. The first network adapter is operable to transmit each portion together with identifying information and information identifying a location for storing the transmitted portion in the memory of the second node, such that each portion is capable of being received independently by the second node according to the identifying information. Each portion is further capable of being stored in the memory of the second node at the location identified by the location identifying information.
摘要翻译：提供了一种远程直接存储器访问（RDMA）系统，其中通过DMA在具有由网络连接的多个节点的多处理器系统的第一节点的存储器和第二个存储器连接的存储器之间的网络上通过网络传送数据多处理器系统的节点。该系统包括第一节点处的第一网络适配器，可操作以在DMA请求的多个部分中将存储在第一节点的存储器中的数据发送到多个部分中的第二节点。第一网络适配器可操作以将每个部分与识别信息和信息一起发送，识别信息和信息标识用于存储第二节点的存储器中的发送部分的位置，使得每个部分能够由第二节点独立地根据识别信息。每个部分还能够在由位置识别信息标识的位置处存储在第二节点的存储器中。

6. 发明申请

US20070097875A1 Efficient probabilistic duplicate packet detector in computer networks 失效
标题翻译：计算机网络中的高效概率重复数据包检测器
公开(公告)号：US20070097875A1
公开(公告)日：2007-05-03
申请号：US11264529
申请日：2005-11-01
申请人： Carl Bender , Fu Chang , Kevin Gildea , Rama Govindaraju , Jay Herring , Peter Hochschild , Richard Swetz
发明人： Carl Bender , Fu Chang , Kevin Gildea , Rama Govindaraju , Jay Herring , Peter Hochschild , Richard Swetz
IPC分类号： H04L12/26
CPC分类号： H04L29/06 , H04L1/0057 , H04L1/0061 , H04L1/0079 , H04L69/326 , H04L2001/0092
摘要： In order to solve the problem of the detection of the arrival of duplicate data packets in an interconnected, multinode data processing system, each data packet is provided with a field of r bits that are randomly generated for each data packet. However, one of the packets is provided with a field that is computed from the other randomly generated field entries in a checksum computation which yields a selected nonzero checksum value. A running checksum at the receiver is used to determine whether or not, after the receipt of the specified number, k, of data packets, a duplicate packet has been received.
摘要翻译：为了解决在互连的多节点数据处理系统中检测到重复数据分组的问题的问题，每个数据分组被提供有为每个数据分组随机生成的r比特的字段。然而，其中一个分组被提供有一个字段，该字段是在产生选定的非零校验和值的校验和计算中的其他随机生成的字段条目中计算的。在接收机上运行的校验和用于确定在接收到数据包的指定数量k之后是否已经接收到重复分组。

7. 发明申请

US20050097300A1 Processing system and method including a dedicated collective offload engine providing collective processing in a distributed computing environment 审中-公开
标题翻译：处理系统和方法包括在分布式计算环境中提供集体处理的专用集合卸载引擎
公开(公告)号：US20050097300A1
公开(公告)日：2005-05-05
申请号：US10697859
申请日：2003-10-30
申请人： Kevin Gildea , Rama Govindaraju , Peter Hochschild
发明人： Kevin Gildea , Rama Govindaraju , Peter Hochschild
IPC分类号： G06F9/50 , G06F15/00
CPC分类号： G06F9/5066 , G06F2209/509
摘要： A dedicated collective offload engine provides collective processing of data from processing nodes in a distributed computing environment. The dedicated collective offload engine and the processing nodes are coupled to a switch fabric. A result is produced by the collective offload engine based on the collective processing of the data, and is forwarded to at least one processing node. Collective processing is facilitated by communication among a plurality of dedicated collective offload engines via the switch fabric or via a private channel disposed between the collective offload engines.
摘要翻译：专用的集体卸载引擎在分布式计算环境中提供来自处理节点的数据的集体处理。专用集体卸载引擎和处理节点耦合到交换结构。结果是由集体卸载引擎基于数据的集合处理产生的，并被转发到至少一个处理节点。通过经由交换结构的多个专用集合卸载发动机之间的通信或经由设置在集体卸载发动机之间的专用通道进行通信来促进集体处理。

8. 发明申请

US20070150659A1 Cache injection semi-synchronous memory copy operation 失效
标题翻译：缓存注入半同步内存复制操作
公开(公告)号：US20070150659A1
公开(公告)日：2007-06-28
申请号：US11316070
申请日：2005-12-22
申请人： Ravi Arimilli , Rama Govindaraju , Peter Hochschild , Bruce Mealey , Satya Sharma , Balaram Sinharoy
发明人： Ravi Arimilli , Rama Govindaraju , Peter Hochschild , Bruce Mealey , Satya Sharma , Balaram Sinharoy
IPC分类号： G06F12/00
CPC分类号： G06F9/30032 , G06F9/3004 , G06F9/30087 , G06F9/383 , G06F9/3834 , G06F12/0862 , G06F12/0888 , G06F12/0897 , G06F2212/6028
摘要： A system, method, and a computer readable for inserting data into a cache memory based on information in a semi-synchronous memory copy instruction are disclosed. The method comprises determining a start of a semi-synchronous memory copy operation. The semi-synchronous memory copy operation is checked for a given value in at least one cache injection bit. In response to the given value in the cache injection bit, a predefined number of lines of destination data is copied into at least one level of cache memory.
摘要翻译：公开了一种基于半同步存储器复制指令中的信息将数据插入高速缓冲存储器的系统，方法和计算机。该方法包括确定半同步存储器复制操作的开始。在至少一个高速缓存注入位中检查给定值的半同步存储器复制操作。响应于高速缓存注入位中的给定值，预定数量的目的地数据行被复制到至少一级的高速缓存存储器中。

9. 发明授权

US07774554B2 System and method for intelligent software-controlled cache injection 失效
标题翻译：用于智能软件控制缓存注入的系统和方法
公开(公告)号：US07774554B2
公开(公告)日：2010-08-10
申请号：US11676745
申请日：2007-02-20
申请人： Piyush Chaudhary , Rama K. Govindaraju , Jay Robert Herring , Peter Hochschild , Chulho Kim , Rajeev Sivaram , Hanhong Xue
发明人： Piyush Chaudhary , Rama K. Govindaraju , Jay Robert Herring , Peter Hochschild , Chulho Kim , Rajeev Sivaram , Hanhong Xue
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F12/0817
摘要： A system and method to provide injection of important data directly into a processor's cache location when that processor has previously indicated interest in the data. The memory subsystem at a target processor will determine if the memory address of data to be written to a memory location associated with the target processor is found in a processor cache of the target processor. If it is determined that the memory address is found in a target processor's cache, the data will be directly written to that cache at the same time that the data is being provided to a location in main memory.
摘要翻译：当处理器先前已经对数据感兴趣时，提供将重要数据直接注入处理器的高速缓存位置的系统和方法。目标处理器上的存储器子系统将确定是否在目标处理器的处理器高速缓存中找到要写入到与目标处理器相关联的存储器位置的数据的存储器地址。如果确定在目标处理器的高速缓存中找到存储器地址，则在将数据提供给主存储器中的位置的同时，数据将被直接写入该高速缓存。

10. 发明申请

US20070150676A1 Efficient and flexible memory copy operation 失效
标题翻译：高效灵活的内存复制操作
公开(公告)号：US20070150676A1
公开(公告)日：2007-06-28
申请号：US11316663
申请日：2005-12-22
申请人： Ravi Arimilli , Rama Govindaraju , Peter Hochschild , Bruce Mealey , Satya Sharma , Balaram Sinharoy
发明人： Ravi Arimilli , Rama Govindaraju , Peter Hochschild , Bruce Mealey , Satya Sharma , Balaram Sinharoy
IPC分类号： G06F12/16
CPC分类号： G06F9/3834 , G06F9/3004 , G06F9/3824
摘要： A system, method, and computer program product for semi-synchronously copying data from a first portion of memory to a second portion of memory are disclosed. The method comprises receiving, in a processor, a call for a semi-synchronous memory copy operation. The semi-synchronous memory copy operation preserves temporal persistence of validity for a virtual source address corresponding to a source location in a memory and a virtual target address corresponding to a target location in the memory by setting a flag bit. The call includes at least the virtual source address, the virtual target address, and an indicator identifying a number of bytes to be copied. The memory copy operation is placed in a queue for execution by a memory controller. The queue is coupled to the memory controller. At least one subsequent instruction is continued to be executed as the subsequent instruction becomes available from an instruction pipeline.
摘要翻译：公开了一种用于将数据从存储器的第一部分半数同步地复制到存储器的第二部分的系统，方法和计算机程序产品。该方法包括在处理器中接收对半同步存储器复制操作的呼叫。半同步存储器复制操作通过设置标志位来保持对应于存储器中的源位置的虚拟源地址和对应于存储器中的目标位置的虚拟目标地址的有效性的时间持续性。该呼叫至少包括虚拟源地址，虚拟目标地址和标识要复制的字节数的指示符。存储器复制操作被放置在队列中以由存储器控制器执行。队列耦合到存储器控制器。随着随后的指令从指令流水线可用，继续执行至少一个后续指令。

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