专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06434049B1 Sample and hold voltage reference source 有权
标题翻译：采样和保持电压参考源
公开(公告)号：US06434049B1
公开(公告)日：2002-08-13
申请号：US09753354
申请日：2000-12-29
申请人： Ritesh Trivedi , Robert Baltar , Mark Bauer , Sandeep Guliani , Balaji Srinivasan
发明人： Ritesh Trivedi , Robert Baltar , Mark Bauer , Sandeep Guliani , Balaji Srinivasan
IPC分类号： G11C1606
CPC分类号： G11C27/024 , G11C16/28
摘要： An apparatus and method are disclosed for providing a sample and hold voltage reference for non-volatile memory. According to one embodiment, the sample and hold voltage reference produces a reference voltage for a drain bias circuit of a memory cell.
摘要翻译：公开了用于为非易失性存储器提供采样和保持电压基准的装置和方法。根据一个实施例，采样和保持电压基准产生用于存储器单元的漏极偏置电路的参考电压。

2. 发明授权

US06570789B2 Load for non-volatile memory drain bias 有权
标题翻译：负载用于非易失性存储器漏极偏置
公开(公告)号：US06570789B2
公开(公告)日：2003-05-27
申请号：US09752535
申请日：2000-12-29
申请人： Ritesh Trivedi , Robert Baltar , Mark Bauer , Sandeep Guliani , Balaji Srinivasan
发明人： Ritesh Trivedi , Robert Baltar , Mark Bauer , Sandeep Guliani , Balaji Srinivasan
IPC分类号： G11C1606
CPC分类号： G11C16/28 , G11C16/24
摘要： An apparatus is disclosed for providing a load for a non-volatile memory drain bias circuit. Under an embodiment, a load for a non-volatile memory drain bias circuit comprises a column load and a current mirror, a reference voltage for the current mirror being a sample and hold voltage reference. The column load and the current mirror are coupled to a cascode device.
摘要翻译：公开了一种用于为非易失性存储器漏极偏置电路提供负载的装置。在一个实施例中，用于非易失性存储器漏极偏置电路的负载包括列负载和电流镜，电流镜的参考电压是采样和保持电压基准。列负载和电流镜耦合到共源共栅器件。

3. 发明授权

US06744671B2 Kicker for non-volatile memory drain bias 有权
标题翻译： Kicker用于非易失性存储器漏极偏置
公开(公告)号：US06744671B2
公开(公告)日：2004-06-01
申请号：US09752550
申请日：2000-12-29
申请人： Ritesh Trivedi , Robert Baltar , Mark Bauer , Sandeep Guliani , Balajl Srinivasan
发明人： Ritesh Trivedi , Robert Baltar , Mark Bauer , Sandeep Guliani , Balajl Srinivasan
IPC分类号： G11C1606
CPC分类号： G11C16/24 , G11C16/28
摘要： An apparatus and method are disclosed for providing a kicker function for non-volatile memory drain bias. According to one embodiment, the kicker function is provided by a high performance transistor that is activated by a kicker enable signal, providing a kicker function for non-volatile memory drain bias. According to one embodiment, the kicker function is provided by a high performance transistor that is activated by a kicker enable signal.
摘要翻译：公开了一种用于为非易失性存储器漏极偏置提供踢球功能的装置和方法。根据一个实施例，通过由猝发器使能信号激活的高性能晶体管提供踢icker功能，为非易失性存储器漏极偏置提供踢击功能。根据一个实施例，通过由启动器使能信号激活的高性能晶体管来提供启动器功能。

4. 发明授权

US06535423B2 Drain bias for non-volatile memory 失效
公开(公告)号：US06535423B2
公开(公告)日：2003-03-18
申请号：US09752370
申请日：2000-12-29
申请人： Ritesh Trivedi , Robert Baltar , Mark Bauer , Sandeep Guliani , Balaji Srinivasan
发明人： Ritesh Trivedi , Robert Baltar , Mark Bauer , Sandeep Guliani , Balaji Srinivasan
IPC分类号： G11C700
CPC分类号： G11C16/24 , G11C16/28
摘要： An apparatus and method are disclosed for providing drain bias for non-volatile memory. According to one embodiment, the drain bias is provided utilizing a drain bias circuit that is referenced by a static voltage reference.

5. 发明授权

US06456540B1 Method and apparatus for gating a global column select line with address transition detection 失效
标题翻译：用于选通具有地址转换检测的全局列选择行的方法和装置
公开(公告)号：US06456540B1
公开(公告)日：2002-09-24
申请号：US09773140
申请日：2001-01-30
申请人： Robert Baltar , Ritesh Trivedi
发明人： Robert Baltar , Ritesh Trivedi
IPC分类号： G11C700
CPC分类号： G11C16/24 , G11C7/1048 , G11C16/28
摘要： A method and apparatus for a memory device is described. In one embodiment, global Y (GY) enable is gated by the trailing edge of a address transition detection (ATD) pulse. The ATD pulse ensures that the GY enable is off during periods when the memory device is not attempting to read a memory cell. The sense (SEN) node between the GY transistor and drain bias circuit may be charged up and global bit line (GBL) may be grounded. During this time, the power supply current is cut off by the GY transistor itself, thereby eliminating the need of separate cut-off transistors within the drain bias circuit. This permits minimal time delay in sensing after the incoming address is stable.
摘要翻译：描述了一种用于存储器件的方法和装置。在一个实施例中，全局Y（GY）使能由地址转换检测（ATD）脉冲的后沿选通。 ATD脉冲确保在存储器件未尝试读取存储器单元的周期期间GY使能关闭。 GY晶体管和漏极偏置电路之间的感测（SEN）节点可能被充电，并且全局位线（GBL）可能接地。在这段时间内，电源电流被GY晶体管本身截止，从而消除了在漏极偏置电路内分离的截止晶体管的需要。这在传入地址稳定后允许最小的检测时间延迟。

6. 发明授权

US09104547B2 Wear leveling for a memory device 有权
标题翻译：对于存储设备的磨损均衡
公开(公告)号：US09104547B2
公开(公告)日：2015-08-11
申请号：US13197460
申请日：2011-08-03
申请人： Robert Baltar
发明人： Robert Baltar
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7211 , G11C11/5628 , G11C16/0483 , G11C16/3495
摘要： Memory devices and methods to facilitate wear leveling operations in a memory device. In one such method, particular blocks of memory cells are excluded from experiencing wear leveling operations performed on the memory device. In at least one method, a user selects blocks of memory to be excluded from wear leveling operations performed on the remainder of blocks of the memory device. Selected blocks of memory are excluded from wear leveling operations responsive to a command initiated by a user identifying, either directly or indirectly, the selected blocks to be excluded.
摘要翻译：用于促进存储器件中的磨损均衡操作的存储器件和方法。在一种这样的方法中，特定的存储器单元块被排除在经历在存储器件上执行的磨损均衡操作之外。在至少一种方法中，用户从存储器件的剩余块执行的磨损均衡操作中选择要排除的存储器块。响应于用户发起的命令直接或间接地识别要排除的所选择的块，所选择的存储块被排除在磨损均衡操作之外。

7. 发明申请

US20130036253A1 WEAR LEVELING FOR A MEMORY DEVICE 有权
标题翻译：为记忆设备而磨损
公开(公告)号：US20130036253A1
公开(公告)日：2013-02-07
申请号：US13197460
申请日：2011-08-03
申请人： Robert Baltar
发明人： Robert Baltar
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7211 , G11C11/5628 , G11C16/0483 , G11C16/3495
摘要： Memory devices and methods to facilitate wear leveling operations in a memory device. In one such method, particular blocks of memory cells are excluded from experiencing wear leveling operations performed on the memory device. In at least one method, a user selects blocks of memory to be excluded from wear leveling operations performed on the remainder of blocks of the memory device. Selected blocks of memory are excluded from wear leveling operations responsive to a command initiated by a user identifying, either directly or indirectly, the selected blocks to be excluded.
摘要翻译：用于促进存储器件中的磨损均衡操作的存储器件和方法。在一种这样的方法中，特定的存储器单元块被排除在经历在存储器件上执行的磨损均衡操作之外。在至少一种方法中，用户从存储器件的剩余块执行的磨损均衡操作中选择要排除的存储器块。响应于用户发起的命令直接或间接地识别要排除的所选择的块，所选存储器块被排除在磨损均衡操作之外。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式