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    • 1. 发明授权
    • Vision coprocessing
    • 视觉协同处理
    • US5793899A
    • 1998-08-11
    • US567454
    • 1995-12-05
    • Robert Anthony WolffSteven Mark RosenthalWilliam Michael SilverJean-Pierre Schott
    • Robert Anthony WolffSteven Mark RosenthalWilliam Michael SilverJean-Pierre Schott
    • G06T5/20G06K9/40
    • G06T5/20
    • A coprocessor in an image processing system is coupled to the bus to which a CPU and RAM holding image data are also coupled. The coprocessor extracts an input pixel stream corresponding to input images from selected bus transactions, performs computations on the input stream to produce output pixel streams corresponding to output images, and inserts the output pixel streams into selected CPU-to-memory bus transactions so that the memory stores the data. The CPU generates the selected bus transactions with specially marked address and/or control signals. The coprocessor includes a lookup table, and a first row delay. The row delay accumulates the three most recent rows of input pixels, which are sent to Sobel and rank processing sections for neighborhood processing. The results are thresholded and formatted, and are either output directly or passed through an additional pair of row delays to accumulate three rows of result data for neighborhood peak detection.
    • 图像处理系统中的协处理器耦合到总线,CPU和RAM保持图像数据也被耦合到总线上。 协处理器从所选择的总线事务中提取与输入图像相对应的输入像素流,对输入流执行计算,以产生与输出图像相对应的输出像素流,并将输出像素流插入到选定的CPU到存储器总线事务中, 内存存储数据。 CPU通过特别标记的地址和/或控制信号生成所选择的总线事务。 协处理器包括查找表和第一行延迟。 行延迟累积输入像素的三个最近行,其被发送到Sobel和等级处理部分用于邻域处理。 结果被阈值化和格式化,或者直接输出或通过附加的一对行延迟,以累积三行用于邻域峰值检测的结果数据。
    • 2. 发明授权
    • Vision coprocessing
    • 视觉协同处理
    • US5657403A
    • 1997-08-12
    • US891955
    • 1992-06-01
    • Robert Anthony WolffSteven Mark RosenthalWilliam Michael SilverJean-Pierre Schott
    • Robert Anthony WolffSteven Mark RosenthalWilliam Michael SilverJean-Pierre Schott
    • G06T5/20G06K9/54G06K9/60
    • G06T5/20
    • A coprocessor in an image processing system is coupled to the bus to which a CPU and RAM holding image data are also coupled. The coprocessor extracts an input pixel stream corresponding to input images from selected bus transactions, performs computations on the input stream to produce output pixel streams corresponding to output images, and inserts the output pixel streams into selected CPU-to-memory bus transactions so that the memory stores the data. The CPU generates the selected bus transactions with specially marked address and/or control signals. The coprocessor includes a lookup table, and a first row delay. The row delay accumulates the three most recent rows of input pixels, which are sent to Sobel and rank processing sections for neighborhood processing. The results are thresholded and formatted, and are either output directly or passed through an additional pair of row delays to accumulate three rows of result data for neighborhood peak detection.
    • 图像处理系统中的协处理器耦合到总线,CPU和RAM保持图像数据也被耦合到总线上。 协处理器从所选择的总线事务中提取与输入图像相对应的输入像素流,对输入流执行计算,以产生与输出图像相对应的输出像素流,并将输出像素流插入到选定的CPU到存储器总线事务中, 内存存储数据。 CPU通过特别标记的地址和/或控制信号生成所选择的总线事务。 协处理器包括查找表和第一行延迟。 行延迟累积输入像素的三个最近行,其被发送到Sobel和等级处理部分用于邻域处理。 结果被阈值化和格式化,或者直接输出或通过附加的一对行延迟,以累积三行用于邻域峰值检测的结果数据。