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1. 发明申请

US20060101356A1 TECHNOLOGY MIGRATION FOR INTEGRATED CIRCUITS WITH RADICAL DESIGN RESTRICTIONS 有权
标题翻译：用于具有放射性设计限制的集成电路的技术移动
公开(公告)号：US20060101356A1
公开(公告)日：2006-05-11
申请号：US10904225
申请日：2004-10-29
申请人： Robert Allen , Cam Endicott , Fook-Luen Heng , Jason Hibbeler , Kevin McCullen , Rani Narayan , Robert Walker , Xin Yuan
发明人： Robert Allen , Cam Endicott , Fook-Luen Heng , Jason Hibbeler , Kevin McCullen , Rani Narayan , Robert Walker , Xin Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5068
摘要： A method, system and program product for migrating an integrated circuit (IC) design from a source technology without radical design restrictions (RDR) to a target technology with RDR, are disclosed. The invention implements a minimum layout perturbation approach that addresses the RDR requirements. The invention also solves the problem of inserting dummy shapes where required, and extending the lengths of the critical shapes and/or the dummy shapes to meet ‘edge coverage’ requirements.
摘要翻译：公开了一种用于将集成电路（IC）设计从没有激进设计限制（RDR）的源技术迁移到具有RDR的目标技术的方法，系统和程序产品。本发明实现了解决RDR要求的最小布局扰动方法。本发明还解决了在需要时插入虚拟形状的问题，并且延伸临界形状和/或虚拟形状的长度以满足“边缘覆盖”要求。

2. 发明申请

US20070198961A1 TECHNOLOGY MIGRATION FOR INTEGRATED CIRCUITS WITH RADICAL DESIGN RESTRICTIONS 失效
标题翻译：用于具有放射性设计限制的集成电路的技术移动
公开(公告)号：US20070198961A1
公开(公告)日：2007-08-23
申请号：US11697798
申请日：2007-04-09
申请人： Robert Allen , Cam Endicott , Fook-Luen Heng , Jason Hibbeler , Kevin McCullen , Rani Narayan , Robert Walker , Xin Yuan
发明人： Robert Allen , Cam Endicott , Fook-Luen Heng , Jason Hibbeler , Kevin McCullen , Rani Narayan , Robert Walker , Xin Yuan
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5077 , G06F17/5068
摘要： A method, system and program product for migrating an integrated circuit (IC) design from a source technology without radical design restrictions (RDR) to a target technology with RDR, are disclosed. Also, a method, system and program product for migrating an integrated circuit design from a source technology without RDR to a target technology with RDR in which space may be reserved for late insertion of a feature and in which migration first occurs in a primary compaction direction having less tolerant ground rules.
摘要翻译：公开了一种用于将集成电路（IC）设计从没有激进设计限制（RDR）的源技术迁移到具有RDR的目标技术的方法，系统和程序产品。另外，一种用于将集成电路设计从没有RDR的源技术迁移到具有RDR的目标技术的方法，系统和程序产品，其中可以保留用于后期插入特征的空间，并且首先在初始压实方向上发生迁移具有较差的基本规则。

3. 发明申请

US20070277129A1 TECHNOLOGY MIGRATION FOR INTEGRATED CIRCUITS WITH RADICAL DESIGN RESTRICTIONS 失效
标题翻译：用于具有放射性设计限制的集成电路的技术移动
公开(公告)号：US20070277129A1
公开(公告)日：2007-11-29
申请号：US11837732
申请日：2007-08-13
申请人： Robert Allen , Cam Endicott , Fook-Luen Heng , Jason Hibbeler , Kevin McCullen , Rani Narayan , Robert Walker , Xin Yuan
发明人： Robert Allen , Cam Endicott , Fook-Luen Heng , Jason Hibbeler , Kevin McCullen , Rani Narayan , Robert Walker , Xin Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5068
摘要： A method, system and program product for migrating an integrated circuit (IC) design from a source technology without radical design restrictions (RDR) to a target technology with RDR, are disclosed. The invention implements a minimum layout perturbation approach that addresses the RDR requirements. The invention also solves the problem of inserting dummy shapes where required, and extending the lengths of the critical shapes and/or the dummy shapes to meet ‘edge coverage’ requirements.
摘要翻译：公开了一种用于将集成电路（IC）设计从没有激进设计限制（RDR）的源技术迁移到具有RDR的目标技术的方法，系统和程序产品。本发明实现了解决RDR要求的最小布局扰动方法。本发明还解决了在需要时插入虚拟形状的问题，并且延伸临界形状和/或虚拟形状的长度以满足“边缘覆盖”要求。

4. 发明申请

US20060101357A1 TECHNOLOGY MIGRATION FOR INTEGRATED CIRCUITS WITH RADICAL DESIGN RESTRICTIONS 有权
标题翻译：用于具有放射性设计限制的集成电路的技术移动
公开(公告)号：US20060101357A1
公开(公告)日：2006-05-11
申请号：US10905008
申请日：2004-12-09
申请人： Robert Allen , Cam Endicott , Fook-Luen Heng , Jason Hibbeler , Kevin McCullen , Rani Narayan , Robert Walker , Xin Yuan
发明人： Robert Allen , Cam Endicott , Fook-Luen Heng , Jason Hibbeler , Kevin McCullen , Rani Narayan , Robert Walker , Xin Yuan
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5068
摘要： A method, system and program product for migrating an integrated circuit (IC) design from a source technology without radical design restrictions (RDR) to a target technology with RDR, are disclosed. Also, a method, system and program product for migrating an integrated circuit design from a source technology without RDR to a target technology with RDR in which space may be reserved for late insertion of a feature and in which migration first occurs in a primary compaction direction having less tolerant ground rules.
摘要翻译：公开了一种用于将集成电路（IC）设计从没有激进设计限制（RDR）的源技术迁移到具有RDR的目标技术的方法，系统和程序产品。另外，一种用于将集成电路设计从没有RDR的源技术迁移到具有RDR的目标技术的方法，系统和程序产品，其中可以保留用于后期插入特征的空间，并且首先在初始压实方向上发生迁移具有较差的基本规则。

5. 发明申请

US20060085768A1 INTEGRATED CIRCUIT SELECTIVE SCALING 有权
标题翻译：集成电路选择性缩放
公开(公告)号：US20060085768A1
公开(公告)日：2006-04-20
申请号：US10711959
申请日：2004-10-15
申请人： Fook-Luen Heng , Jason Hibbeler , Kevin McCullen , Rani Narayan , Stephen Runyon , Robert Walker
发明人： Fook-Luen Heng , Jason Hibbeler , Kevin McCullen , Rani Narayan , Stephen Runyon , Robert Walker
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Methods, systems and program products are disclosed for selectively scaling an integrated circuit (IC) design: by layer, by unit, or by ground rule, or a combination of these. The selective scaling technique can be applied in a feedback loop with the manufacturing system with process and yield feedback, during the life of a design, to increase yield in early processes in such a way that hierarchy is preserved. The invention removes the need to involve designers in improving yield where new technologies such as maskless fabrication are implemented.
摘要翻译：公开了用于选择性地缩放集成电路（IC）设计的方法，系统和程序产品：按层，单元或基本规则，或这些的组合。在设计寿命期间，选择性缩放技术可以应用于具有过程和产量反馈的制造系统的反馈回路中，以便以保持层次结构的方式增加早期过程中的产量。本发明消除了在实现诸如无掩模制造之类的新技术的情况下使设计人员改进产量的需要。

6. 发明申请

US20070245283A1 MINIMUM LAYOUT PERTURBATION-BASED ARTWORK LEGALIZATION WITH GRID CONSTRAINTS FOR HIERARCHICAL DESIGNS 失效
标题翻译：用于分层设计的网格约束的最小布局基于假设的艺术品法规
公开(公告)号：US20070245283A1
公开(公告)日：2007-10-18
申请号：US11279758
申请日：2006-04-14
申请人： Robert Allen , Michael Gray , Fuok-Luen Heng , Jason Hibbeler , Kevin McCullen , Rani Narayan , Robert Walker
发明人： Robert Allen , Michael Gray , Fuok-Luen Heng , Jason Hibbeler , Kevin McCullen , Rani Narayan , Robert Walker
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method comprises extracting a hierarchical grid constraint set and modeling one or more critical objects of at least one cell as a variable set. The method further comprises solving a linear programming problem based on the hierarchical grid constraint set with the variable set to provide initial locations of the critical objects of the at least one cell and determining target on-grid locations of the one or more critical objects in the at least one cell using the results of the linear programming solution.
摘要翻译：一种方法包括提取分级网格约束集合并将至少一个小区的一个或多个关键对象建模为变量集。该方法还包括基于具有变量集合的分级网格约束集来解决线性规划问题，以提供至少一个小区的关键对象的初始位置并且确定所述至少一个小区中的一个或多个关键对象的目标并网位置使用线性规划解决方案的结果的至少一个小区。

7. 发明申请

US20050160390A1 CLONED AND ORIGINAL CIRCUIT SHAPE MERGING 失效
标题翻译：克隆和原始电路形状合并
公开(公告)号：US20050160390A1
公开(公告)日：2005-07-21
申请号：US10707845
申请日：2004-01-16
申请人： Henry Bonges , Michael Gray , Jason Hibbeler , Kevin McCullen , Robert Walker
发明人： Henry Bonges , Michael Gray , Jason Hibbeler , Kevin McCullen , Robert Walker
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method, system and program product for merging cloned and original circuit shapes such that a union thereof does not include a notch. The invention determines, for a cell including an original circuit shape and at least one overlapping clone of the original circuit shape, whether each clone corner point of each overlapping clone is within a threshold distance of a corresponding original corner point of the original circuit shape; and generates, in the case that each clone corner point of each overlapping clone circuit shape is within a threshold distance, a union of each overlapping clone and the original circuit shape such that the union does not contain a notch. The union is generated using a point code that sets a new position for a union corner point to remove a notch based on the original shape's direction and the edge orientations previous to and next to the corner point.
摘要翻译：用于合并克隆和原始电路形状的方法，系统和程序产品，使得其联合不包括缺口。本发明对于包括原始电路形状的单元和原始电路形状的至少一个重叠克隆来确定每个重叠克隆的每个克隆角点是否处于原始电路形状的相应原始角点的阈值距离内; 并且在每个重叠克隆电路形状的每个克隆角点处于阈值距离内的情况下，生成每个重叠克隆的结合和原始电路形状，使得联合不包含凹口。联合是使用点代码生成的，该点代码为联合角点设置新位置，以根据原始形状的方向和角点之前和之后的边缘方向去除凹口。

8. 发明申请

US20060150130A1 INTEGRATED CIRCUIT YIELD ENHANCEMENT USING VORONOI DIAGRAMS 有权
标题翻译：使用VORONOI DIAGRAMS的集成电路增益
公开(公告)号：US20060150130A1
公开(公告)日：2006-07-06
申请号：US10709292
申请日：2004-04-27
申请人： Robert Allen , Michael Gray , Jason Hibbeler , Mervyn Tan , Robert Walker
发明人： Robert Allen , Michael Gray , Jason Hibbeler , Mervyn Tan , Robert Walker
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5081
摘要： A method of calculating critical area in an integrated circuit design, said method comprising: inputting an integrated circuit design; associating variables with the positions of edges in said integrated circuit design; and associating cost functions of said variables with spacing between said edges in said integrated circuit design; wherein said cost functions calculate critical area contributions as the positions and length of said edges in said integrated circuit design change, and wherein said critical area contributions comprise a measure of electrical fault characteristics of said spacing between said edges in said integrated circuit design.
摘要翻译：一种在集成电路设计中计算临界面积的方法，所述方法包括：输入集成电路设计; 将变量与所述集成电路设计中的边缘的位置相关联; 以及将所述变量的成本函数与所述集成电路设计中的所述边缘之间的间隔相关联; 其中当所述集成电路设计中的所述边缘的位置和长度改变时，所述成本函数计算临界面积贡献，并且其中所述临界区域贡献包括所述集成电路设计中所述边缘之间的所述间隔的电气故障特征的量度。

9. 发明申请

US20050240884A1 VIA SPACING VIOLATION CORRECTION METHOD, SYSTEM AND PROGRAM PRODUCT 审中-公开
标题翻译：通过空间暴露校正方法，系统和程序产品
公开(公告)号：US20050240884A1
公开(公告)日：2005-10-27
申请号：US10709294
申请日：2004-04-27
申请人： Terry Frederick , Jason Hibbeler , Kevin McCullen , William Pokorny
发明人： Terry Frederick , Jason Hibbeler , Kevin McCullen , William Pokorny
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5068
摘要： A method, system and program product for correcting via spacing violations by generating a redundant via to replace one of a pair of vias that violate a ground rule, are disclosed. The redundant via corrects the ground rule violation. The target via corresponding to the redundant via is then removed, which corrects the ground rule violation. The invention can be applied to any spacing ground rule including same net and different net rules, and may also be applied to a current technology or, during migration, to a new technology. The invention can be applied to different levels of a design to ensure ground rule compliance throughout the design.
摘要翻译：公开了一种用于通过产生冗余通道来更换间隔违规的方法，系统和程序产品，以替代违反基本规则的一对通孔中的一个。冗余通道修正了基本规则违规。然后删除对应于冗余通道的目标，这校正了违反基本规则的行为。本发明可以应用于包括相同网络和不同网络规则的任何间隔地面规则，并且还可以应用于当前技术，或者在迁移期间应用于新技术。本发明可以应用于不同级别的设计，以确保整个设计中的基本规则符合性。

10. 发明申请

US20060064661A1 Method and system for obtaining a feasible integer solution from a half-integer solution in hierarchical circuit layout optimization 有权
公开(公告)号：US20060064661A1
公开(公告)日：2006-03-23
申请号：US10946677
申请日：2004-09-22
申请人： Michael Gray , Jason Hibbeler , Gustavo Tellez , Robert Walker
发明人： Michael Gray , Jason Hibbeler , Gustavo Tellez , Robert Walker
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5068
摘要： A method (300) and system (500) for optimizing a circuit layout based on layout constraints (308) and objectives (312). The method includes solving a linear program so as to obtain a rational solution whose variables are either whole or half integer. The tight constraints and objectives involving variables whose solution are a half integer are reduced to a 2-SAT problem, which is analyzed to determine its satisfiability. If the 2-SAT problem is not satisfiable, one or more objectives are removed so as to make the 2-SAT problem satisfiable. Any half-integer results of the linear program are rounded according to the truth assignment that satisfies the 2-SAT problem. The rounded results are used to create the circuit layout.

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