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1. 发明授权

US09024326B2 Method and design of an RF thru-via interconnect 有权
标题翻译：射频通孔互连的方法和设计
公开(公告)号：US09024326B2
公开(公告)日：2015-05-05
申请号：US13879696
申请日：2012-07-18
申请人： Robert Actis , Pane-chane Chao , Robert J. Lender, Jr. , Kanin Chu , Bernard J. Schmanski , Sue May Jessup
发明人： Robert Actis , Pane-chane Chao , Robert J. Lender, Jr. , Kanin Chu , Bernard J. Schmanski , Sue May Jessup
IPC分类号： H01L29/15 , H01L23/373 , H01L23/66 , H01L23/48
CPC分类号： H01L23/373 , H01L23/481 , H01L23/66 , H01L2223/6622 , H01L2223/6627 , H01L2224/4847 , H01L2924/10272 , H01L2924/1033 , H01L2924/1421 , H01L2924/3011 , H01L2924/30111 , H01L2924/00
摘要： In summary, a vertical metalized transition in the form of a via goes from the back side of a high thermal conductivity substrate and through any semiconductor layers thereon to a patterned metalized strip, with the substrate having a patterned metalized layer on the back side that is provided with a keep away zone dimensioned to provide impedance matching for RF energy coupled through the substrate to the semiconductor device while at the same time permitting the heat generated by the semiconductor device to flow through the high thermal conductivity substrate, through the back side of the substrate and to a beat sink.
摘要翻译：总而言之，以通孔形式的垂直金属化转变从高导热性衬底的背面开始并通过其上的任何半导体层到图案化的金属化带，衬底在背面具有图案化的金属化层，具有保留区，其尺寸设置成为通过衬底耦合到半导体器件的RF能量提供阻抗匹配，同时允许由半导体器件产生的热量流过高导热性衬底，通过该衬底的背面底物和一个水槽。

2. 发明申请

US20120208359A1 Structure And Method For Fabrication Of Field Effect Transistor Gates With Or Without Field Plates 有权
标题翻译：具有或不具有场板的场效应晶体管门极的结构和方法
公开(公告)号：US20120208359A1
公开(公告)日：2012-08-16
申请号：US13150359
申请日：2011-06-01
申请人： Anthony A. Immorlica , Pane-chane Chao , Kanin Chu
发明人： Anthony A. Immorlica , Pane-chane Chao , Kanin Chu
IPC分类号： H01L21/283
CPC分类号： H01L29/402 , H01L29/2003 , H01L29/42316 , H01L29/66462
摘要： A method for fabrication of a field effect transistor gate, with or without field plates, includes the steps of defining a relatively thin Schottky metal layer by a lithography/metal liftoff or metal deposition/etch process on a semiconductor surface. This is followed by depositing a dielectric passivation layer over the entire wafer and defining a second lithographic pattern coincident with or slightly inset from the boundaries of the previously defined metal gate layer. This is followed by etching the dielectric using dry or wet etching techniques and stripping the resist, followed by exposing and developing a third resist pattern to define the thicker gate metal layers required for electrical conductivity and also for the field plate if one is utilized. The final step is depositing gate and/or field plate metal, resulting in a gate electrode and an integral field plate.
摘要翻译：用于制造具有或不具有场板的场效应晶体管栅极的方法包括以下步骤：通过在半导体表面上的光刻/金属剥离或金属沉积/蚀刻工艺限定相对较薄的肖特基金属层。之后，在整个晶片上沉积介电钝化层，并且限定与先前限定的金属栅极层的边界重合或略微插入的第二光刻图案。然后使用干蚀刻或湿蚀刻技术蚀刻电介质并剥离抗蚀剂，随后暴露和显影第三抗蚀剂图案以限定电导率所需的较厚的栅极金属层，以及如果使用的话，也可用于场板。最后一步是沉积栅极和/或场板金属，产生栅电极和整体场板。

3. 发明授权

US08003504B2 Structure and method for fabrication of field effect transistor gates with or without field plates 有权
标题翻译：具有或不具有场板的场效应晶体管栅极的制造的结构和方法
公开(公告)号：US08003504B2
公开(公告)日：2011-08-23
申请号：US12086854
申请日：2007-08-31
申请人： Anthony A. Immorlica , Pane-chane Chao , Kanin Chu
发明人： Anthony A. Immorlica , Pane-chane Chao , Kanin Chu
IPC分类号： H01L21/28
CPC分类号： H01L29/402 , H01L29/2003 , H01L29/42316 , H01L29/66462
摘要： A method for fabrication of a field effect transistor gate, with or without field plates, includes the steps of defining a relatively thin Schottky metal layer by a lithography/metal liftoff or metal deposition/etch process on a semiconductor surface. This is followed by depositing a dielectric passivation layer over the entire wafer and defining a second lithographic pattern coincident with or slightly inset from the boundaries of the previously defined metal gate layer. This is followed by etching the dielectric using dry or wet etching techniques and stripping the resist, followed by exposing and developing a third resist pattern to define the thicker gate metal layers required for electrical conductivity and also for the field plate if one is utilized. The final step is depositing gate and/or field plate metal, resulting in a gate electrode and an integral field plate.
摘要翻译：用于制造具有或不具有场板的场效应晶体管栅极的方法包括以下步骤：通过在半导体表面上的光刻/金属剥离或金属沉积/蚀刻工艺限定相对较薄的肖特基金属层。之后，在整个晶片上沉积介电钝化层，并且限定与先前限定的金属栅极层的边界重合或略微插入的第二光刻图案。然后使用干蚀刻或湿蚀刻技术蚀刻电介质并剥离抗蚀剂，随后暴露和显影第三抗蚀剂图案以限定电导率所需的较厚的栅极金属层，以及如果使用的话，也可用于场板。最后一步是沉积栅极和/或场板金属，产生栅电极和整体场板。

4. 发明授权

US08304332B2 Structure and method for fabrication of field effect transistor gates with or without field plates 有权
标题翻译：具有或不具有场板的场效应晶体管栅极的制造的结构和方法
公开(公告)号：US08304332B2
公开(公告)日：2012-11-06
申请号：US13150359
申请日：2011-06-01
申请人： Anthony A. Immorlica , Pane-chane Chao , Kanin Chu
发明人： Anthony A. Immorlica , Pane-chane Chao , Kanin Chu
IPC分类号： H01L21/28
CPC分类号： H01L29/402 , H01L29/2003 , H01L29/42316 , H01L29/66462
摘要： A method for fabrication of a field effect transistor gate, with or without field plates, includes the steps of defining a relatively thin Schottky metal layer by a lithography/metal liftoff or metal deposition/etch process on a semiconductor surface. This is followed by depositing a dielectric passivation layer over the entire wafer and defining a second lithographic pattern coincident with or slightly inset from the boundaries of the previously defined metal gate layer. This is followed by etching the dielectric using dry or wet etching techniques and stripping the resist, followed by exposing and developing a third resist pattern to define the thicker gate metal layers required for electrical conductivity and also for the field plate if one is utilized. The final step is depositing gate and/or field plate metal, resulting in a gate electrode and an integral field plate.
摘要翻译：用于制造具有或不具有场板的场效应晶体管栅极的方法包括以下步骤：通过在半导体表面上的光刻/金属剥离或金属沉积/蚀刻工艺限定相对较薄的肖特基金属层。之后，在整个晶片上沉积介电钝化层，并且限定与先前限定的金属栅极层的边界重合或略微插入的第二光刻图案。然后使用干蚀刻或湿蚀刻技术蚀刻电介质并剥离抗蚀剂，随后暴露和显影第三抗蚀剂图案以限定电导率所需的较厚的栅极金属层，以及如果使用的话，也可用于场板。最后一步是沉积栅极和/或场板金属，产生栅电极和整体场板。

5. 发明申请

US20120205726A1 Structure And Method For Fabrication Of Field Effect Transistor Gates With Or Without Field Plates 审中-公开
公开(公告)号：US20120205726A1
公开(公告)日：2012-08-16
申请号：US13150352
申请日：2011-06-01
申请人： Anthony A. Immorlica , Pane-chane Chao , Kanin Chu
发明人： Anthony A. Immorlica , Pane-chane Chao , Kanin Chu
IPC分类号： H01L29/812
CPC分类号： H01L29/402 , H01L29/2003 , H01L29/42316 , H01L29/66462
摘要： A method for fabrication of a field effect transistor gate, with or without field plates, includes the steps of defining a relatively thin Schottky metal layer by a lithography/metal liftoff or metal deposition/etch process on a semiconductor surface. This is followed by depositing a dielectric passivation layer over the entire wafer and defining a second lithographic pattern coincident with or slightly inset from the boundaries of the previously defined metal gate layer. This is followed by etching the dielectric using dry or wet etching techniques and stripping the resist, followed by exposing and developing a third resist pattern to define the thicker gate metal layers required for electrical conductivity and also for the field plate if one is utilized. The final step is depositing gate and/or field plate metal, resulting in a gate electrode and an integral field plate.

6. 发明申请

US20100301395A1 Asymmetrically recessed high-power and high-gain ultra-short gate HEMT device 有权
标题翻译：不对称凹陷的大功率和高增益超短栅HEMT器件
公开(公告)号：US20100301395A1
公开(公告)日：2010-12-02
申请号：US12462515
申请日：2009-08-05
申请人： Dong Xu , Xiaoping Yang , Wendell Kong , Lee M. Mohnkern , Phillip M. Smith , Pane-chane Chao
发明人： Dong Xu , Xiaoping Yang , Wendell Kong , Lee M. Mohnkern , Phillip M. Smith , Pane-chane Chao
IPC分类号： H01L29/778 , H01L21/335
CPC分类号： H01L29/66431 , H01L29/7784 , H01L29/7785
摘要： A high-power and high-gain ultra-short gate HEMT device has exceptional gain and an exceptionally high breakdown voltage provided by an increased width asymmetric recess for the gate electrode, by a composite channel layer including a thin indium arsenide layer embedded in the indium gallium arsenide channel layer and by double doping through the use of an additional silicon doping spike. The improved transistor has an exceptional 14 dB gain at 110 GHz and exhibits an exceptionally high 3.5-4 V breakdown voltage, thus to provide high gain, high-power and ultra-high frequency in an ultra-short gate device.
摘要翻译：高功率和高增益超短栅极HEMT器件具有特别的增益和由栅极电极的增加宽度不对称凹槽提供的异常高的击穿电压，通过复合沟道层，其包括嵌入在铟中的薄的砷化铟层砷化镓沟道层，并通过使用额外的硅掺杂尖峰进行双掺杂。改进的晶体管在110 GHz时具有超强的14 dB增益，并具有极高的3.5-4 V击穿电压，从而在超短栅极器件中提供高增益，大功率和超高频。

7. 发明申请

US20080241757A1 Reproducible, high yield method for fabricating ultra-short T-gates on HFETs 有权
标题翻译：用于在HFET上制造超短T型栅极的可再现的高产率方法
公开(公告)号：US20080241757A1
公开(公告)日：2008-10-02
申请号：US12079529
申请日：2008-03-27
申请人： Dong Xu , Gabriel Cueva , Pane-chane Chao , Wendell Kong
发明人： Dong Xu , Gabriel Cueva , Pane-chane Chao , Wendell Kong
IPC分类号： G03F7/20
CPC分类号： H01L21/28581 , H01L21/0272
摘要： A method for fabricating ultra-short T-gates on heterojunction field effect transistors (HFETs) comprising the steps of (a) providing a coating of three layers of resists, with polymethylmethacrylate (PMMA) with high molecular weight on the bottom, polydimethylglutarimide (PMGI) in the middle, and PMMA with low molecular weight on the top; (b) in a first exposure, exposing and developing the layers with a dose of a developer that is high enough to allow the developer to break the top PMMA but low to avoid contributing significantly to the overall dose received in the bottom PMMA layer; and (c) in a second exposure, using an exposure and developing process to define 0.03-0.05 um openings in the bottom PMMA layer.
摘要翻译：一种用于在异质结场效应晶体管（HFET）上制造超短T栅极的方法，包括以下步骤：（a）提供三层抗蚀剂的涂层与底部具有高分子量的聚甲基丙烯酸甲酯（PMMA），聚二甲基戊二酰亚胺（PMGI ），顶部分子量低的PMMA; （b）在第一次曝光中，用一定剂量的显影剂曝光和显影层，以使得显影剂能够破坏顶部PMMA但是低，以避免对底部PMMA层中所接收的总剂量产生显着影响; 和（c）在第二次曝光中，使用曝光和显影过程在底部PMMA层中限定0.03-0.05μm的开口。

8. 发明授权

US07943286B2 Reproducible, high yield method for fabricating ultra-short T-gates on HFETs 有权
标题翻译：用于在HFET上制造超短T型栅极的可再现的高产率方法
公开(公告)号：US07943286B2
公开(公告)日：2011-05-17
申请号：US12079529
申请日：2008-03-27
申请人： Dong Xu , Gabriel Cueva , Pane-chane Chao , Wendell Kong
发明人： Dong Xu , Gabriel Cueva , Pane-chane Chao , Wendell Kong
IPC分类号： G03F7/26
CPC分类号： H01L21/28581 , H01L21/0272
摘要： A method for fabricating ultra-short T-gates on heterojunction field effect transistors (HFETs) comprising the steps of (a) providing a coating of three layers of resists, with polymethylmethacrylate (PMMA) with high molecular weight on the bottom, polydimethylglutarimide (PMGI) in the middle, and PMMA with low molecular weight on the top; (b) in a first exposure, exposing and developing the layers with a dose of a developer that is high enough to allow the developer to break the top PMMA but low to avoid contributing significantly to the overall dose received in the bottom PMMA layer; and (c) in a second exposure, using an exposure and developing process to define 0.03-0.05 um openings in the bottom PMMA layer.
摘要翻译：一种用于在异质结场效应晶体管（HFET）上制造超短T栅极的方法，包括以下步骤：（a）提供三层抗蚀剂的涂层与底部具有高分子量的聚甲基丙烯酸甲酯（PMMA），聚二甲基戊二酰亚胺（PMGI ），顶部分子量低的PMMA; （b）在第一次曝光中，用一定剂量的显影剂曝光和显影层，以使得显影剂能够破坏顶部PMMA但是低，以避免对底部PMMA层中所接收的总剂量产生显着影响; 和（c）在第二次曝光中，使用曝光和显影过程在底部PMMA层中限定0.03-0.05μm的开口。

9. 发明授权

US08445941B2 Asymmetrically recessed high-power and high-gain ultra-short gate HEMT device 有权
公开(公告)号：US08445941B2
公开(公告)日：2013-05-21
申请号：US12462515
申请日：2009-08-05
申请人： Dong Xu , Xiaoping S. Yang , Wendell Kong , Lee M. Mohnkern , Phillip M. Smith , Pane-chane Chao
发明人： Dong Xu , Xiaoping S. Yang , Wendell Kong , Lee M. Mohnkern , Phillip M. Smith , Pane-chane Chao
IPC分类号： H01L21/335 , H01L29/778
CPC分类号： H01L29/66431 , H01L29/7784 , H01L29/7785
摘要： A high-power and high-gain ultra-short gate HEMT device has exceptional gain and an exceptionally high breakdown voltage provided by an increased width asymmetric recess for the gate electrode, by a composite channel layer including a thin indium arsenide layer embedded in the indium gallium arsenide channel layer and by double doping through the use of an additional silicon doping spike. The improved transistor has an exceptional 14 dB gain at 110 GHz and exhibits an exceptionally high 3.5-4 V breakdown voltage, thus to provide high gain, high-power and ultra-high frequency in an ultra-short gate device.

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