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1. 发明授权

US06303275B1 Method for resist filling and planarization of high aspect ratio features 失效
标题翻译：高宽比特征的抗蚀剂填充和平坦化方法
公开(公告)号：US06303275B1
公开(公告)日：2001-10-16
申请号：US09501653
申请日：2000-02-10
申请人： Robert A. Coles , John W. Golz , Qinghuang Lin , Alan C. Thomas , Christopher J. Waskiewicz , Teresa J. Wu
发明人： Robert A. Coles , John W. Golz , Qinghuang Lin , Alan C. Thomas , Christopher J. Waskiewicz , Teresa J. Wu
IPC分类号： G03C500
CPC分类号： G03F7/16 , G03F7/168
摘要： A method of forming a resist layer of uniform thickness across a surface patterned with a varying density of high aspect ratio features. A selected material layer having an affinity to a resist coat to be applied over the selected material layer is applied to a wafer having a plurality of recesses before applying a resist coat. After the resist coat is applied over the selected material layer, the selected material diffuses partially into the resist coat to condition a portion of the resist coat to be insoluble in the presence of a developer which is applied after the resist coat. Those portions of the resist coat into which the selected material layer has not diffused then are removed by a developer leaving a uniform resist coat thickness across the wafer.
摘要翻译：一种形成均匀厚度的抗蚀剂层的方法，该抗蚀剂层跨越具有不同密度的高纵横比特征的图案化的表面。在施加抗蚀剂涂层之前，将具有与要涂覆在所选择的材料层上的抗蚀剂涂层具有亲和性的所选材料层施加到具有多个凹部的晶片上。在抗蚀剂涂层施加在所选择的材料层上之后，所选择的材料部分地扩散到抗蚀剂涂层中，以使抗蚀剂涂层的一部分在抗蚀剂涂层之后施加的显影剂的存在下不溶。所选择的材料层未被扩散的抗蚀剂涂层的那些部分被显影剂除去，在晶片上留下均匀的抗蚀剂涂层厚度。

2. 发明授权

US06294449B1 Self-aligned contact for closely spaced transistors 失效
标题翻译：紧密间隔晶体管的自对准触点
公开(公告)号：US06294449B1
公开(公告)日：2001-09-25
申请号：US09447627
申请日：1999-11-23
申请人： Teresa J. Wu , Bomy A. Chen , John W. Golz , Charles W. Koburger, III , Paul C. Parries , Christopher J. Waskiewicz , Jin Jwang Wu
发明人： Teresa J. Wu , Bomy A. Chen , John W. Golz , Charles W. Koburger, III , Paul C. Parries , Christopher J. Waskiewicz , Jin Jwang Wu
IPC分类号： H01L2144
CPC分类号： H01L21/76897
摘要： A pair of transistors sharing a common electrodes e.g. a bitline in a DRAM array, has a self-aligned contact to the bitline in which the transistor gate stack has only a poly layer with a nitride cover; the aperture for the bitline contact is time-etched to penetrate only between the gates and not reach the silicon substrate; exposed nitride shoulders of the gate are etched to expose the poly; the remainder of the interlayer dielectric is removed by a selective etch; the exposed poly is re-oxidized to protect the gates; and the aperture bottom is cleaned; so that the thick gate stack of a DRAM is dispensed with in order to improve uniformity of line width across the chip beyond what the DRAM technique can deliver.
摘要翻译：一对共用共用电极的晶体管 DRAM阵列中的位线具有与位线的自对准接触，其中晶体管栅极堆叠仅具有具有氮化物覆盖层的多晶硅层; 用于位线接触的孔径被时间刻蚀以仅在栅极之间穿透而不到达硅衬底; 蚀刻栅极的暴露的氮化物肩部以暴露多晶硅; 通过选择性蚀刻去除层间电介质的其余部分; 暴露的聚合物被再氧化以保护浇口; 并清洁孔径底部; 从而不需要DRAM的厚栅堆叠，以便提高跨芯片的线宽的均匀性，超出了DRAM技术可以传送的范围。

3. 发明授权

US06845033B2 Structure and system-on-chip integration of a two-transistor and two-capacitor memory cell for trench technology 失效
标题翻译：用于沟槽技术的双晶体管和双电容器存储单元的结构和片上系统集成
公开(公告)号：US06845033B2
公开(公告)日：2005-01-18
申请号：US10248954
申请日：2003-03-05
申请人： Toshiaki Kirihata , John W. Golz
发明人： Toshiaki Kirihata , John W. Golz
IPC分类号： H01L27/108 , G11C11/24 , G11C11/401 , G11C11/404 , H01L21/8242
CPC分类号： G11C11/404 , H01L27/108 , H01L27/10829
摘要： A two-port dynamic random access memory (DRAM) cell consisting of two transistors and two trench capacitors (2T and 2C DRAM cell) connecting two one transistor and one capacitor DRAM cell (1T DRAM cell) is described. The mask data and cross-section of the 2T 2C DRAM and 1T DRAM cells are fully compatible to each other except for the diffusion connection that couples two storage nodes of the two 1T DRAM cells. This allows a one-port memory cell with 1T and 1C DRAM cell and a two-port memory cell with 2T and 2C DRAM cell to be fully integrated, forming a true system-on chip architecture. Alternatively, by halving the capacitor, the random access write cycle time is further reduced, while still maintaining the data retention time. The deep trench process time is also reduced by reducing by one-half the trench depth.
摘要翻译：描述了连接两个晶体管和一个电容器DRAM单元（1T DRAM单元）的两个晶体管和两个沟槽电容器（2T和2C DRAM单元）组成的双端口动态随机存取存储器（DRAM）单元。除了连接两个1T DRAM单元的两个存储节点的扩散连接之外，2T 2C DRAM和1T DRAM单元的掩模数据和横截面彼此完全兼容。这允许具有1T和1C DRAM单元的单端口存储器单元和具有2T和2C DRAM单元的双端口存储器单元被完全集成，形成真正的片上系统体系结构。或者，通过将电容器减半，随机存取写周期时间进一步降低，同时仍然保持数据保留时间。深沟槽加工时间也减少了沟槽深度的一半。

4. 发明授权

US06816397B1 Bi-directional read write data structure and method for memory 有权
标题翻译：双向读写数据结构和存储方法
公开(公告)号：US06816397B1
公开(公告)日：2004-11-09
申请号：US10448776
申请日：2003-05-29
申请人： John W. Golz , David R. Hanson , Hoki Kim
发明人： John W. Golz , David R. Hanson , Hoki Kim
IPC分类号： G11C502
CPC分类号： G11C7/1057 , G11C7/1051 , G11C7/1078 , G11C7/1084 , G11C11/4093
摘要： As disclosed herein, an integrated circuit memory is provided which includes primary sense amplifiers coupled for access to a multiplicity of storage cells, second sense amplifiers, and pairs of input/output data lines (IODLs), each IODL pair being coupled to a primary sense amplifier, and each IODL pair carrying complementary signals representing a storage bit. The memory further includes pairs of bi-directional primary data lines (BPDLs), each BPDL pair being coupled to a second sense amplifier and each BPDL pair being adapted to carry other complementary signals representing a storage bit. Local buffers are adapted to transfer, in accordance with control input, the complementary signals carried by the IODLs to the BPDLs, and vice versa.
摘要翻译：如本文所公开的，提供集成电路存储器，其包括被耦合用于访问多个存储单元，第二读出放大器和输入/输出数据线对（IODL）的初级读出放大器，每个IODL对被耦合到主感测放大器和每个IODL对承载表示存储位的互补信号。存储器还包括成对的双向主数据线（BPDL），每个BPDL对被耦合到第二读出放大器，并且每个BPDL对适于承载表示存储位的其他互补信号。本地缓冲器适于根据控制输入将IODL携带的互补信号传送到BPDL，反之亦然。

5. 发明授权

US06768143B1 Structure and method of making three finger folded field effect transistors having shared junctions 失效
标题翻译：制造具有共同连接点的三指折叠场效应晶体管的结构和方法
公开(公告)号：US06768143B1
公开(公告)日：2004-07-27
申请号：US10604913
申请日：2003-08-26
申请人： Gregory J. Fredeman , John W. Golz , David R. Hanson , Hoki Kim
发明人： Gregory J. Fredeman , John W. Golz , David R. Hanson , Hoki Kim
IPC分类号： H01L2710
CPC分类号： H01L27/10897 , G11C11/4085
摘要： An integrated circuit including a field effect transistor (FET) is provided in which the gate conducter has an even number of fingers disposed between alternating source and drain regions of a substrate. The fingers are disposed in a pattern over an area of the substrate having a length in a horizontal direction, the area equaling the length multiplied by a width in a vertical direction that is occupied by an odd number of the fingers.
摘要翻译：提供了包括场效应晶体管（FET）的集成电路，其中栅极导通器具有设置在衬底的交替的源极和漏极区域之间的偶数个指状物。手指在图案上设置有在水平方向上具有长度的区域的区域，该区域等于长度乘以由奇数手指占据的垂直方向上的宽度。

6. 发明授权

US07046572B2 Low power manager for standby operation of memory system 有权
标题翻译：低功耗管理器用于存储系统的待机操作
公开(公告)号：US07046572B2
公开(公告)日：2006-05-16
申请号：US10250233
申请日：2003-06-16
申请人： David R. Hansen , Gregory J. Fredeman , John W. Golz , Hoki Kim , Paul C. Parries
发明人： David R. Hansen , Gregory J. Fredeman , John W. Golz , Hoki Kim , Paul C. Parries
IPC分类号： G11C7/00
CPC分类号： G11C5/143 , G11C8/08
摘要： A memory system includes a memory array, a plurality of wordline drivers, a row address decoder block which has a plurality of outputs connected to selected ones of the wordline drivers, a row selector block which has a selector lines connected to individual ones of the wordline drivers. A power management circuit having a power down input for a power down input signal (WLPWRDN) and a wordline power down output (WLPDN) is connected to the wordline drivers to lower the power consumption thereof as a function of the power down input signal.
摘要翻译：存储器系统包括存储器阵列，多个字线驱动器，行地址解码器块，其具有连接到所选择的字线驱动器的多个输出;行选择器块，其具有连接到字线的各个字符的选择器线司机。具有用于断电输入信号（WLPWRDN）和字线掉电输出（WLPDN）的掉电输入的功率管理电路被连接到字线驱动器，以根据掉电输入信号降低其功耗。

7. 发明授权

US07023758B2 Low power manager for standby operation of a memory system 有权
标题翻译：低功耗管理器用于存储系统的待机操作
公开(公告)号：US07023758B2
公开(公告)日：2006-04-04
申请号：US11205565
申请日：2005-08-17
申请人： David R. Hanson , Gregory J Fredeman , John W. Golz , Hoki Kim , Paul C. Parries
发明人： David R. Hanson , Gregory J Fredeman , John W. Golz , Hoki Kim , Paul C. Parries
IPC分类号： G11C7/00
CPC分类号： G11C5/143 , G11C8/08
摘要： A memory system includes a memory array, a plurality of wordline drivers, a row address decoder block which has a plurality of outputs connected to selected ones of the wordline drivers, a row selector block which has a selector lines connected to individual ones of the wordline drivers. A power management circuit having a power down input for a power down input signal (WLPWRDN) and a wordline power down output (WLPDN) is connected to the wordline drivers to lower the power consumption thereof as a function of the power down input signal.
摘要翻译：存储器系统包括存储器阵列，多个字线驱动器，行地址解码器块，其具有连接到所选择的字线驱动器的多个输出;行选择器块，其具有连接到字线的各个字符的选择器线司机。具有用于断电输入信号（WLPWRDN）和字线掉电输出（WLPDN）的掉电输入的功率管理电路被连接到字线驱动器，以根据掉电输入信号降低其功耗。

8. 发明授权

US06747890B1 Gain cell structure with deep trench capacitor 有权
标题翻译：具有深沟槽电容器的增益单元结构
公开(公告)号：US06747890B1
公开(公告)日：2004-06-08
申请号：US10249347
申请日：2003-04-02
申请人： Toshiaki Kirihata , Subramanian S. Iyer , John W. Golz
发明人： Toshiaki Kirihata , Subramanian S. Iyer , John W. Golz
IPC分类号： G11C1124
CPC分类号： H01L27/10844 , G11C2207/104 , H01L27/108 , H01L27/11
摘要： Gain cells adapted to trench capacitor technology and memory array configured with these gain cells are described. The 3T and 2T gain cells of the present invention include a trench capacitor attached to a storage node such that the storage voltage is maintained for a long retention time. The gate of the gain transistor and the trench capacitor are placed alongside the read and write wordline. This arrangement makes it possible to have the gain transistor directly coupled to the trench capacitor, resulting in a smaller cell size. The memory cell includes a first transistor provided with a gate, a source, and a drain respectively coupled to a read wordline, a first node, and a read bitline; a second transistor having a gate, a source, and a drain respectively coupled to a storage node, to a voltage source, and to the first node; a third transistor having a gate, a source, and a drain respectively coupled to a write wordline, the storage node, and a write bitline; and a capacitor having a first terminal connected to the storage node and a second terminal connected to a voltage source.
摘要翻译：描述适用于沟槽电容器技术的增益单元和配置有这些增益单元的存储器阵列。本发明的3T和2T增益单元包括连接到存储节点的沟槽电容器，使得存储电压保持长的保留时间。增益晶体管的栅极和沟槽电容器放置在读写字线旁边。这种布置使得可以使增益晶体管直接耦合到沟槽电容器，导致更小的单元尺寸。存储单元包括：第一晶体管，其设置有分别耦合到读字线，第一节点和读位线的栅极，源极和漏极; 第二晶体管，其具有分别耦合到存储节点的栅极，源极和漏极，电压源以及所述第一节点; 第三晶体管，具有分别耦合到写入字线，存储节点和写入位线的栅极，源极和漏极; 以及电容器，其具有连接到存储节点的第一端子和连接到电压源的第二端子。

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