专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08022549B2 Standard cell and semiconductor device including the same 有权
标题翻译：包括其的标准单元和半导体器件
公开(公告)号：US08022549B2
公开(公告)日：2011-09-20
申请号：US12947344
申请日：2010-11-16
申请人： Ritsuko Ozoe , Hiroki Taniguchi , Hidetoshi Nishimura , Masaki Tamaru , Hideaki Kondo
发明人： Ritsuko Ozoe , Hiroki Taniguchi , Hidetoshi Nishimura , Masaki Tamaru , Hideaki Kondo
IPC分类号： H01L23/52
CPC分类号： H01L27/11807 , H01L27/0207
摘要： This invention prevents a break in a signal wire disposed between wire ends due to attenuation and improves production yields of devices. In a standard cell, a first signal wire extends in a first direction. Second and third signal wires extend in a second direction substantially perpendicular to the first direction and are facing each other across the first signal wire. The second and third signal wires have the widths larger than the width of the first signal wire.
摘要翻译：本发明防止由于衰减引起的布线在线端之间的信号线断裂，并且提高了器件的产量。在标准单元中，第一信号线在第一方向上延伸。第二和第三信号线在基本上垂直于第一方向的第二方向上延伸并且跨越第一信号线彼此面对。第二和第三信号线的宽度大于第一信号线的宽度。

2. 发明申请

US20080246160A1 STANDARD CELL AND SEMICONDUCTOR DEVICE INCLUDING THE SAME 有权
标题翻译：包括其的标准单元和半导体器件
公开(公告)号：US20080246160A1
公开(公告)日：2008-10-09
申请号：US12098035
申请日：2008-04-04
申请人： Ritsuko Ozoe , Hiroki Taniguchi , Hidetoshi Nishimura , Masaki Tamaru , Hideaki Kondo
发明人： Ritsuko Ozoe , Hiroki Taniguchi , Hidetoshi Nishimura , Masaki Tamaru , Hideaki Kondo
IPC分类号： H01L23/52
CPC分类号： H01L27/11807 , H01L27/0207
摘要： This invention prevents a break in a signal wire disposed between wire ends due to attenuation and improves production yields of devices. In a standard cell, a first signal wire extends in a first direction. Second and third signal wires extend in a second direction substantially perpendicular to the first direction and are facing each other across the first signal wire. The second and third signal wires have the widths larger than the width of the first signal wire.
摘要翻译：本发明防止由于衰减引起的布线在线端之间的信号线断裂，并且提高了器件的产量。在标准单元中，第一信号线在第一方向上延伸。第二和第三信号线在基本上垂直于第一方向的第二方向上延伸并且跨越第一信号线彼此面对。第二和第三信号线的宽度大于第一信号线的宽度。

3. 发明授权

US08143724B2 Standard cell and semiconductor device including the same 有权
标题翻译：包括其的标准单元和半导体器件
公开(公告)号：US08143724B2
公开(公告)日：2012-03-27
申请号：US13211130
申请日：2011-08-16
申请人： Ritsuko Ozoe , Hiroki Taniguchi , Hidetoshi Nishimura , Masaki Tamaru , Hideaki Kondo
发明人： Ritsuko Ozoe , Hiroki Taniguchi , Hidetoshi Nishimura , Masaki Tamaru , Hideaki Kondo
IPC分类号： H01L23/52
CPC分类号： H01L27/11807 , H01L27/0207
摘要： This invention prevents a break in a signal wire disposed between wire ends due to attenuation and improves production yields of devices. In a standard cell, a first signal wire extends in a first direction. Second and third signal wires extend in a second direction substantially perpendicular to the first direction and are facing each other across the first signal wire. The second and third signal wires have the widths larger than the width of the first signal wire.
摘要翻译：本发明防止由于衰减引起的布线在线端之间的信号线断裂，并且提高了器件的产量。在标准单元中，第一信号线在第一方向上延伸。第二和第三信号线在基本上垂直于第一方向的第二方向上延伸并且跨越第一信号线彼此面对。第二和第三信号线的宽度大于第一信号线的宽度。

4. 发明申请

US20110298138A1 STANDARD CELL AND SEMICONDUCTOR DEVICE INCLUDING THE SAME 有权
公开(公告)号：US20110298138A1
公开(公告)日：2011-12-08
申请号：US13211130
申请日：2011-08-16
申请人： Ritsuko OZOE , Hiroki Taniguchi , Hidetoshi Nishimura , Masaki Tamaru , Hideaki Kondo
发明人： Ritsuko OZOE , Hiroki Taniguchi , Hidetoshi Nishimura , Masaki Tamaru , Hideaki Kondo
IPC分类号： H01L23/52
CPC分类号： H01L27/11807 , H01L27/0207
摘要： This invention prevents a break in a signal wire disposed between wire ends due to attenuation and improves production yields of devices. In a standard cell, a first signal wire extends in a first direction. Second and third signal wires extend in a second direction substantially perpendicular to the first direction and are facing each other across the first signal wire. The second and third signal wires have the widths larger than the width of the first signal wire.

5. 发明授权

US07859023B2 Standard cell and semiconductor device including the same 有权
标题翻译：包括其的标准单元和半导体器件
公开(公告)号：US07859023B2
公开(公告)日：2010-12-28
申请号：US12098035
申请日：2008-04-04
申请人： Ritsuko Ozoe , Hiroki Taniguchi , Hidetoshi Nishimura , Masaki Tamaru , Hideaki Kondo
发明人： Ritsuko Ozoe , Hiroki Taniguchi , Hidetoshi Nishimura , Masaki Tamaru , Hideaki Kondo
IPC分类号： H01L27/10
CPC分类号： H01L27/11807 , H01L27/0207
摘要： This invention prevents a break in a signal wire disposed between wire ends due to attenuation and improves production yields of devices. In a standard cell, a first signal wire extends in a first direction. Second and third signal wires extend in a second direction substantially perpendicular to the first direction and are facing each other across the first signal wire. The second and third signal wires have the widths larger than the width of the first signal wire.
摘要翻译：本发明防止由于衰减引起的布线在线端之间的信号线断裂，并且提高了器件的产量。在标准单元中，第一信号线在第一方向上延伸。第二和第三信号线在基本上垂直于第一方向的第二方向上延伸并且跨越第一信号线彼此面对。第二和第三信号线的宽度大于第一信号线的宽度。

6. 发明申请

US20110079914A1 STANDARD CELL AND SEMICONDUCTOR DEVICE INCLUDING THE SAME 有权
标题翻译：包括其的标准单元和半导体器件
公开(公告)号：US20110079914A1
公开(公告)日：2011-04-07
申请号：US12947344
申请日：2010-11-16
申请人： Ritsuko OZOE , Hiroki Taniguchi , Hidetoshi Nishimura , Masaki Tamaru , Hideaki Kondo
发明人： Ritsuko OZOE , Hiroki Taniguchi , Hidetoshi Nishimura , Masaki Tamaru , Hideaki Kondo
IPC分类号： H01L23/52
CPC分类号： H01L27/11807 , H01L27/0207
摘要： This invention prevents a break in a signal wire disposed between wire ends due to attenuation and improves production yields of devices. In a standard cell, a first signal wire extends in a first direction. Second and third signal wires extend in a second direction substantially perpendicular to the first direction and are facing each other across the first signal wire. The second and third signal wires have the widths larger than the width of the first signal wire.
摘要翻译：本发明防止由于衰减引起的布线在线端之间的信号线断裂，并且提高了器件的产量。在标准单元中，第一信号线在第一方向上延伸。第二和第三信号线在基本上垂直于第一方向的第二方向上延伸并且跨越第一信号线彼此面对。第二和第三信号线的宽度大于第一信号线的宽度。

7. 发明授权

US08648392B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US08648392B2
公开(公告)日：2014-02-11
申请号：US12947335
申请日：2010-11-16
申请人： Hidetoshi Nishimura , Masaki Tamaru
发明人： Hidetoshi Nishimura , Masaki Tamaru
IPC分类号： H01L27/118
CPC分类号： H01L27/0207 , H01L27/11807
摘要： A plurality of PMOS transistors are provided on a substrate along an X-axis direction such that a gate length direction of each of the PMOS transistors is parallel to the X-axis direction. A plurality of NMOS transistors are provided on the substrate along the X-axis direction such that a gate length direction of each of the NMOS transistors is parallel to the X-axis direction, and each of the plurality of NMOS transistors is opposed to a corresponding one of the PMOS transistors in the Y-axis direction. Gate lines respectively correspond to the PMOS transistors and the NMOS transistors, and are arranged parallel to each other and extend linearly along the Y-axis direction such that each of the gate lines passes through gate areas of the PMOS transistors and NMOS transistors which correspond to each of the gate lines.
摘要翻译：在X轴方向的基板上设置多个PMOS晶体管，使得PMOS晶体管的栅极长度方向平行于X轴方向。多个NMOS晶体管沿着X轴方向设置在基板上，使得每个NMOS晶体管的栅极长度方向平行于X轴方向，并且多个NMOS晶体管中的每一个与相应的一个PMOS晶体管在Y轴方向上。栅极线分别对应于PMOS晶体管和NMOS晶体管，并且彼此平行地布置并且沿着Y轴方向线性延伸，使得每个栅极线通过PMOS晶体管的栅极区域和对应于每条门线。

8. 发明申请

US20110031536A1 LAYOUT STRUCTURE OF STANDARD CELL, STANDARD CELL LIBRARY, AND LAYOUT STRUCTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：标准单元的布局结构，标准单元库和半导体集成电路的布局结构
公开(公告)号：US20110031536A1
公开(公告)日：2011-02-10
申请号：US12905873
申请日：2010-10-15
申请人： Nana Okamoto , Masaki Tamaru , Hidetoshi Nishimura
发明人： Nana Okamoto , Masaki Tamaru , Hidetoshi Nishimura
IPC分类号： H01L27/118
CPC分类号： H01L23/49827 , H01L27/0207 , H01L27/11807 , H01L2924/0002 , H01L2924/00
摘要： In a layout structure of a standard cell including off transistors 126, 127 unnecessary for logic operation of a circuit, dummy via contacts 116, 117 are disposed on impurity diffusion regions 103, 106 of the off transistors 126, 127, respectively. Dummy metal interconnects 122, 123 are connected to the dummy via contacts 116, 117, respectively. Thus, variations in the density of via contacts, which are one of causes lowering the production yield of semiconductor integrated circuits, is reduced, improving manufacturing defects of the via contacts.
摘要翻译：在不需要电路的逻辑运算的包括截止晶体管126,127的标准单元的布局结构中，虚设通孔触点116,117分别设置在截止晶体管126,127的杂质扩散区域103,106上。虚拟金属互连122,123分别经由触点116,117连接到虚拟电路。因此，降低了半导体集成电路的制造成本的原因之一是通孔接点的密度变化减小，从而改善了通孔接点的制造缺陷。

9. 发明授权

US08766322B2 Layout structure of standard cell, standard cell library, and layout structure of semiconductor integrated circuit 有权
标题翻译：标准单元的布局结构，标准单元库和半导体集成电路的布局结构
公开(公告)号：US08766322B2
公开(公告)日：2014-07-01
申请号：US12905873
申请日：2010-10-15
申请人： Nana Okamoto , Masaki Tamaru , Hidetoshi Nishimura
发明人： Nana Okamoto , Masaki Tamaru , Hidetoshi Nishimura
IPC分类号： H01L27/118 , H01L27/02
CPC分类号： H01L23/49827 , H01L27/0207 , H01L27/11807 , H01L2924/0002 , H01L2924/00
摘要： In a layout structure of a standard cell including off transistors 126, 127 unnecessary for logic operation of a circuit, dummy via contacts 116, 117 are disposed on impurity diffusion regions 103, 106 of the off transistors 126, 127, respectively. Dummy metal interconnects 122, 123 are connected to the dummy via contacts 116, 117, respectively. Thus, variations in the density of via contacts, which are one of causes lowering the production yield of semiconductor integrated circuits, is reduced, improving manufacturing defects of the via contacts.
摘要翻译：在不需要电路的逻辑运算的包括截止晶体管126,127的标准单元的布局结构中，虚设通孔触点116,117分别设置在截止晶体管126,127的杂质扩散区域103,106上。虚拟金属互连122,123分别经由触点116,117连接到虚拟电路。因此，降低了半导体集成电路的制造成本的原因之一是通孔接点的密度变化减小，从而改善了通孔接点的制造缺陷。

10. 发明授权

US08692336B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08692336B2
公开(公告)日：2014-04-08
申请号：US13421010
申请日：2012-03-15
申请人： Masaki Tamaru , Kazuyuki Nakanishi , Hidetoshi Nishimura
发明人： Masaki Tamaru , Kazuyuki Nakanishi , Hidetoshi Nishimura
IPC分类号： H01L27/088
CPC分类号： H01L27/11807 , H01L21/823892 , H01L27/0207 , H01L27/0928 , H01L27/11898 , H01L2027/11866 , H01L2027/11881 , H01L2027/1189
摘要： A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region in the horizontal direction and adjacent gates disposed in further both sides thereof are disposed at the same pitch. In addition, an adjacent cell array includes four gates each of which is opposed to the adjacent gates in the vertical direction. In other words, regularity in the shape of the gate patterns in the periphery of the well potential supply region is maintained.
摘要翻译：在电池阵列的N型阱区域中提供阱电位区域。设置在水平方向上的井电位供给区域的两侧的相邻门和设置在其两侧的相邻门以相同的间距设置。此外，相邻单元阵列包括四个栅极，每个栅极在垂直方向上与相邻栅极相对。换句话说，维持在阱电位供给区域的外围的栅极图案的形状的规则性。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式