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1. 发明授权

US5396466A Method of testing bit lines of a memory unit 失效
标题翻译：测试存储器单元的位线的方法
公开(公告)号：US5396466A
公开(公告)日：1995-03-07
申请号：US214449
申请日：1994-03-17
申请人： Rikizo Nakano , Noriyuki Matsui
发明人： Rikizo Nakano , Noriyuki Matsui
IPC分类号： G11C29/02 , G11C29/10 , G11C7/00
CPC分类号： G11C29/02 , G11C29/10
摘要： A method of testing bit lines of a memory unit includes the steps of alternately writing a set of first binary values and a set of inverted first binary values to blocks having even block values and to blocks having odd block values for all storage elements within each of a plurality of blocks of the memory unit; setting the memory unit to a stressed condition; alternately reading pieces of binary data from first-row storage elements of the blocks having even block values and from final-row storage elements of the blocks having odd block values by repeatedly inverting a row value of a memory address and incrementing a block value of the memory address for each block; setting the memory unit to a normal condition; and repeating the first setting step, the alternate reading step, and the second setting step for all the columns of the plurality of the blocks.
摘要翻译：一种测试存储器单元的位线的方法包括以下步骤：将一组第一二进制值和一组倒置的第一二进制值交替地写入具有偶数块值的块以及具有奇数块值的块，存储单元的多个块; 将存储单元设置为受压状态; 从具有偶数块值的块的第一行存储元件中读取二进制数据，并通过重复地反转存储器地址的行值并递增该块值的块值，并从具有奇数块值的块的最终行存储元件中交替地读取二进制数据每个块的存储器地址; 将存储单元设置为正常状态; 并且对于多个块的所有列重复第一设置步骤，替代阅读步骤和第二设置步骤。

2. 发明授权

US5481551A IC element testing device 失效
标题翻译： IC元件测试装置
公开(公告)号：US5481551A
公开(公告)日：1996-01-02
申请号：US214309
申请日：1994-03-17
申请人： Rikizo Nakano , Noriyuki Matsui
发明人： Rikizo Nakano , Noriyuki Matsui
IPC分类号： G01R31/28 , G01R31/319 , G11C29/00 , G11C29/56 , G06F11/14
CPC分类号： G01R31/31924
摘要： An IC element testing device includes a test pattern generating unit for generating test patterns, a power supply unit for generating a power supply voltage, a superposed voltage generating unit for generating a superposed voltage, and a superposing unit for superposing the superposed voltage on the power supply voltage and for outputting a superposed power supply voltage to an IC element to which the test patterns generated by the test pattern generating unit are applied.
摘要翻译： IC元件测试装置包括用于产生测试图案的测试图形生成单元，用于产生电源电压的电源单元，用于产生叠加电压的叠加电压产生单元和用于将叠加的电压叠加在电源上的叠加单元电源电压并将叠加的电源电压输出到由测试图案生成单元生成的测试图案的IC元件。

3. 发明授权

US07990172B2 Method and apparatus for testing electronic device 失效
标题翻译：电子设备测试方法和装置
公开(公告)号：US07990172B2
公开(公告)日：2011-08-02
申请号：US12556241
申请日：2009-09-09
申请人： Rikizo Nakano
发明人： Rikizo Nakano
IPC分类号： G01R31/34
CPC分类号： G01R31/3004 , G01R31/2837 , G06F11/24 , G11C29/06 , G11C29/56
摘要： An electronic device test method incorporating a stress application step that is effective in screening out infant mortality failures of an electronic device. More specifically, a method for testing an electronic device constructed from a single or a plurality of semiconductor components, includes: turning a power supply on and off repeatedly while changing the ON/OFF cycle and/or voltage value of the power supply that is connected to the electronic device; and verifying whether or not the electronic device operates normally after the power supply has been turned on and off repeatedly.
摘要翻译：一种结合应用应用步骤的电子设备测试方法，其有效地筛选电子设备的婴儿死亡率故障。更具体地说，一种用于测试由单个或多个半导体组件构成的电子设备的方法包括：在改变所连接的电源的ON / OFF周期和/或电压值的同时，重复地打开和关闭电源到电子设备; 并且在电源被反复打开和关闭之后验证电子设备是否正常工作。

4. 发明申请

US20100313086A1 TEST APPARATUS AND TEST METHOD 失效
标题翻译：测试装置和测试方法
公开(公告)号：US20100313086A1
公开(公告)日：2010-12-09
申请号：US12782332
申请日：2010-05-18
申请人： Rikizo Nakano , Osamu Ishibashi , Sadao Miyazaki
发明人： Rikizo Nakano , Osamu Ishibashi , Sadao Miyazaki
IPC分类号： G11C29/04 , G06F11/22
CPC分类号： G11C29/50 , G11C11/401 , G11C29/50012 , G11C29/50016 , G11C29/56 , G11C2029/5002 , G11C2029/5004
摘要： A test apparatus is for testing a memory device including a memory cell. The test apparatus includes a storage and a controller. The storage stores a first value. The controller executes, at a given timing, determining a second value which is a threshold limit value to read data of the memory cell correctly on the basis of an output of the memory cell, calculating a difference between the first value and the second value, outputting a deterioration information on the basis of the difference between the first value and the second value, and updating the first value stored in the storage to the second value.
摘要翻译：测试装置用于测试包括存储器单元的存储器件。测试装置包括存储器和控制器。存储器存储第一个值。控制器在给定的定时执行基于存储器单元的输出来确定作为阈值极限值来正确读取存储器单元的数据的第二值，计算第一值和第二值之间的差值，基于第一值和第二值之间的差异输出劣化信息，并将存储在存储器中的第一值更新为第二值。

5. 发明授权

US08473675B2 Memory system and information processing device 失效
标题翻译：内存系统和信息处理设备
公开(公告)号：US08473675B2
公开(公告)日：2013-06-25
申请号：US12805098
申请日：2010-07-12
申请人： Sadao Miyazaki , Osamu Ishibashi , Rikizo Nakano
发明人： Sadao Miyazaki , Osamu Ishibashi , Rikizo Nakano
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F12/0804 , G06F2212/1016 , G06F2212/1028 , G06F2212/7203 , Y02D10/13
摘要： A memory system includes a first memory that is used as a main memory of a target device, a second memory that has an access speed lower than that of the first memory, a securing section that secures a predetermined area of the first memory as a temporary storage area of the second memory, and a memory control section that receives an instruction to write data into the second memory, temporarily stores the data into the first memory and also transfers the stored data from the first memory to the second memory.
摘要翻译：存储器系统包括用作目标设备的主存储器的第一存储器，具有低于第一存储器存取速度的访问速度的第二存储器，将第一存储器的预定区域固定为临时存储器的固定部件第二存储器的存储区域和接收将数据写入第二存储器的指令的存储器控制部分将数据临时存储到第一存储器中，并将存储的数据从第一存储器传送到第二存储器。

6. 发明授权

US08423842B2 Test apparatus and test method for testing a memory device 失效
标题翻译：用于测试存储器件的测试装置和测试方法
公开(公告)号：US08423842B2
公开(公告)日：2013-04-16
申请号：US12782332
申请日：2010-05-18
申请人： Rikizo Nakano , Osamu Ishibashi , Sadao Miyazaki
发明人： Rikizo Nakano , Osamu Ishibashi , Sadao Miyazaki
IPC分类号： G11C29/00
CPC分类号： G11C29/50 , G11C11/401 , G11C29/50012 , G11C29/50016 , G11C29/56 , G11C2029/5002 , G11C2029/5004
摘要： A test apparatus for testing a memory device including a memory cell. The test apparatus includes a storage and a controller. The storage stores a first value. The controller executes, at a given timing, determining a second value which is a threshold limit value to read data of the memory cell correctly on the basis of an output of the memory cell, calculating a difference between the first value and the second value, outputting a deterioration information on the basis of the difference between the first value and the second value, and updating the first value stored in the storage to the second value.
摘要翻译：一种用于测试包括存储单元的存储器件的测试装置。测试装置包括存储器和控制器。存储器存储第一个值。控制器在给定的定时执行基于存储器单元的输出来确定作为阈值极限值来正确读取存储器单元的数据的第二值，计算第一值和第二值之间的差值，基于第一值和第二值之间的差异输出劣化信息，并将存储在存储器中的第一值更新为第二值。

7. 发明申请

US20110010508A1 Memory system and information processing device 失效
标题翻译：内存系统和信息处理设备
公开(公告)号：US20110010508A1
公开(公告)日：2011-01-13
申请号：US12805098
申请日：2010-07-12
申请人： Sadao Miyazaki , Osamu Ishibashi , Rikizo Nakano
发明人： Sadao Miyazaki , Osamu Ishibashi , Rikizo Nakano
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F12/0804 , G06F2212/1016 , G06F2212/1028 , G06F2212/7203 , Y02D10/13
摘要： A memory system includes a first memory that is used as a main memory of a target device, a second memory that has an access speed lower than that of the first memory, a securing section that secures a predetermined area of the first memory as a temporary storage area of the second memory, and a memory control section that receives an instruction to write data into the second memory, temporarily stores the data into the first memory and also transfers the stored data from the first memory to the second memory.
摘要翻译：存储器系统包括用作目标设备的主存储器的第一存储器，具有低于第一存储器存取速度的访问速度的第二存储器，将第一存储器的预定区域固定为临时存储器的固定部件第二存储器的存储区域和接收将数据写入第二存储器的指令的存储器控制部分将数据临时存储到第一存储器中，并将存储的数据从第一存储器传送到第二存储器。

8. 发明申请

US20070201282A1 Memory module 审中-公开
标题翻译：内存模块
公开(公告)号：US20070201282A1
公开(公告)日：2007-08-30
申请号：US11513225
申请日：2006-08-31
申请人： Rikizo Nakano
发明人： Rikizo Nakano
IPC分类号： G11C5/14
CPC分类号： G11C5/04 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C29/02 , G11C29/022 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A memory module having an array of memory devices, mounted thereon, that operate synchronously with a clock signal, wherein provisions are made to be able to fine-tune the clock phase in accordance with its use conditions. The memory module, having an array of memory devices mounted thereon that operate synchronously with the clock signal, includes; a phase-locked loop circuit which produces an output clock signal adjusted so that the phase of a feedback signal obtained by passing the output clock signal through a feedback loop matches the phase of an input clock signal; and a switching unit which selectively changes a load in the feedback loop in accordance with an external signal.
摘要翻译：一种具有安装在其上的与时钟信号同步操作的存储器件阵列的存储器模块，其中使得能够根据其使用条件微调时钟相位。具有安装在其上的与时钟信号同步工作的存储器件阵列的存储器模块包括：产生输出时钟信号的锁相环电路，所述输出时钟信号被调整为使得通过使输出时钟信号通过反馈环路而获得的反馈信号的相位匹配输入时钟信号的相位; 以及切换单元，其根据外部信号选择性地改变反馈回路中的负载。

9. 发明授权

US08868990B2 Semiconductor memory device and information processing apparatus including the same 有权
标题翻译：半导体存储器件及其信息处理设备
公开(公告)号：US08868990B2
公开(公告)日：2014-10-21
申请号：US13430766
申请日：2012-03-27
申请人： Rikizo Nakano , Osamu Ishibashi , Sadao Miyazaki
发明人： Rikizo Nakano , Osamu Ishibashi , Sadao Miyazaki
IPC分类号： G11C29/00 , G06F13/00 , H03K19/003 , H03K19/094 , G11C29/50 , G11C29/02 , G11C29/04 , G01R31/3187 , G11C29/12 , G11C29/08 , G11C29/14 , H04L25/02
CPC分类号： G11C29/50012 , G01R31/3187 , G11C29/00 , G11C29/02 , G11C29/04 , G11C29/08 , G11C29/12 , G11C29/1201 , G11C29/14 , H04L25/0278
摘要： A semiconductor memory device is disclosed that includes an ODT circuit configured to be connected to a bus which transmits a data signal or a data strobe signal between a memory block and an input-output terminal; a first switch configured to be inserted into the bus between the memory block and the ODT circuit; a mode controller configured to switch off the first switch during a test of the memory block; and an oscillator configured to be connected to the ODT circuit, wherein a test signal is supplied to the ODT circuit from the oscillator during the test of the memory block.
摘要翻译：公开了一种半导体存储器件，其包括被配置为连接到在存储器块和输入 - 输出端子之间传输数据信号或数据选通信号的总线的ODT电路; 第一开关，被配置为插入到所述存储器块和所述ODT电路之间的总线中; 模式控制器，被配置为在所述存储器块的测试期间关闭所述第一开关; 以及配置为连接到ODT电路的振荡器，其中在存储器块的测试期间将测试信号从振荡器提供给ODT电路。

10. 发明授权

US08135971B2 Data processing apparatus 有权
标题翻译：数据处理装置
公开(公告)号：US08135971B2
公开(公告)日：2012-03-13
申请号：US12495991
申请日：2009-07-01
申请人： Sadao Miyazaki , Osamu Ishibashi , Rikizo Nakano , Yoshinori Mesaki
发明人： Sadao Miyazaki , Osamu Ishibashi , Rikizo Nakano , Yoshinori Mesaki
IPC分类号： G06F1/00
CPC分类号： G06F12/0802 , G06F2212/2024 , G06F2212/222 , Y02D10/13
摘要： A data processing apparatus includes a CPU including a register, a cache memory, a main memory configured to exchange data with the cache memory, a control part configured to control the exchanging of data between the main memory and the cache memory, and a power supply part configured to supply power to the register, the cache memory, and the main memory. The register, the cache memory, and the main memory are each configured to store data and maintain the stored data therein without being supplied with the power from the power supply part. The control part is configured to stop the CPU from accessing the register, the cache memory, and the main memory where an abnormality occurs in the power supply part.
摘要翻译：数据处理装置包括：CPU，包括寄存器，高速缓冲存储器，配置为与高速缓存存储器交换数据的主存储器;被配置为控制主存储器和高速缓冲存储器之间的数据交换的控制部分，以及电源配置为向寄存器，高速缓冲存储器和主存储器供电的部件。寄存器，高速缓冲存储器和主存储器都被配置为在不从电源部分提供电力的情况下存储数据并将其保存在其中。控制部被配置为停止CPU访问在电源部中发生异常的寄存器，高速缓冲存储器和主存储器。

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