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1. 发明授权

US4168432A Method of testing radiation hardness of a semiconductor device 失效
标题翻译：测试半导体器件的辐射硬度的方法
公开(公告)号：US4168432A
公开(公告)日：1979-09-18
申请号：US869639
申请日：1978-01-16
申请人： Richard Williams , Murray H. Woods
发明人： Richard Williams , Murray H. Woods
IPC分类号： G01R31/26 , G01T1/24 , G01T1/22
CPC分类号： G01R31/2637
摘要： A body of semiconductor material having a layer of an oxide on a surface thereof is subjected to a negative corona discharge in air to deposit a negative charge on the outer surface of the oxide. This results in an immobile positive charge at the interface between the oxide layer and the semiconductor body. The amount of this positive charge, which can be measured by standard MOS capacitance measurements, indicates the radiation hardness of the device.
摘要翻译：在其表面具有氧化物层的半导体材料体在空气中进行负电晕放电，以在氧化物的外表面上沉积负电荷。这导致在氧化物层和半导体本体之间的界面处具有固定的正电荷。通过标准MOS电容测量可以测量的这种正电荷的量表示器件的辐射硬度。

2. 发明授权

US4307411A Nonvolatile semiconductor memory device and method of its manufacture 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US4307411A
公开(公告)日：1981-12-22
申请号：US873603
申请日：1978-01-30
申请人： James E. Carnes , Murray H. Woods
发明人： James E. Carnes , Murray H. Woods
IPC分类号： H01L21/8247 , H01L29/78 , H01L29/788 , H01L29/792
CPC分类号： H01L29/792 , H01L29/78
摘要： An MNOS nonvolatile semiconductive memory device of the type which has a thick gate insulating layer overlapping the source and drain regions and a thin gate insulator layer in the memory portion of the device includes a region of relatively high concentration of impurities of the same type conductivity as the substrate in the portion of the channel which is beneath the thin gate insulating layer. This increases the values of both the low threshold and the high threshold states of the memory portion of the device so as to increase the threshold voltage window of the device.
摘要翻译：具有与栅极和漏极区重叠的厚栅极绝缘层和器件的存储器部分中的薄栅极绝缘体层的类型的MNOS非易失性半导体存储器件包括具有相同类型导电性的相对高浓度杂质的区域位于薄栅极绝缘层下方的沟道部分中的衬底。这增加了器件的存储器部分的低阈值和高阈值状态的值，以便增加器件的阈值电压窗口。

3. 发明授权

US4236167A Stepped oxide, high voltage MOS transistor with near intrinsic channel regions of different doping levels 失效
标题翻译：步进氧化物，高电压MOS晶体管，具有不同掺杂浓度的近固有沟道区
公开(公告)号：US4236167A
公开(公告)日：1980-11-25
申请号：US875529
申请日：1978-02-06
申请人： Murray H. Woods
发明人： Murray H. Woods
IPC分类号： H01L29/78 , H01L27/12 , H01L29/10 , H01L29/417 , H01L29/423 , H01L29/786
CPC分类号： H01L29/1045 , H01L29/42376 , H01L29/42384 , H01L29/78624
摘要： A Metal-Oxide-Semiconductor-Field-Effect-Transistor (MOSFET) is described wherein a body of semiconductor material is provided with source, drain and channel regions and a gate structure located over the interstitial channel portion of the semiconductor body, between the source and drain regions. A stepped or dual thickness oxide layer, having one portion of minimum thickness formed over only a portion of the channel region and another portion of maximum thickness formed over the remaining portion of the channel region. This stepped oxide layer, together with the gate electrode, forms the gate structure. That portion of the channel region covered by the portion of minimum thickness oxide is separated from the drain region, and the portion of maximum thickness oxide is also located over both a portion of the drain region and that portion of the channel region adjacent the drain region.
摘要翻译：描述了一种金属氧化物半导体场效应晶体管（MOSFET），其中半导体材料体设置有源极，漏极和沟道区域以及位于半导体主体的间隙沟道部分之间的栅极结构，源极和漏区。阶梯状或双重厚度的氧化物层，其仅在沟道区域的一部分上形成最小厚度的一部分，并且在沟道区域的剩余部分上形成最大厚度的另一部分。该阶梯状氧化物层与栅极电极一起形成栅极结构。由最小厚度氧化物的部分覆盖的沟道区域的该部分与漏极区域分离，并且最大厚度氧化物的部分也位于漏极区域的两个部分之上，并且沟道区域的与漏极区域相邻的部分。

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