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1. 发明授权

US06937055B2 Programmable I/O buffer 失效
标题翻译：可编程I / O缓冲器
公开(公告)号：US06937055B2
公开(公告)日：2005-08-30
申请号：US10328907
申请日：2002-12-23
申请人： Richard Stephen Roy , Ali Massoumi , Chao-Wu Chen
发明人： Richard Stephen Roy , Ali Massoumi , Chao-Wu Chen
IPC分类号： H03K19/00 , H04L25/02 , H03K19/003
CPC分类号： H04L25/0278 , H03K19/0005 , H04L25/028 , H04L25/0292
摘要： A programmable input/output buffer has a first plurality of pull-down transistors connected between a supply voltage and an electrical system conductor on the integrated circuit and a second plurality of pull-down transistors connected between the electrical conductor and the system reference voltage. Reference circuits generate signals to turn on a first number of said first plurality of pull-up transistors and/or a second number of said second plurality of pull-down transistors to provide an input/output buffer impedance matching the impedance of the external transmission line either sending a signal to the programmable input/output buffer or receiving a signal from the programmable input/output buffer.
摘要翻译：可编程输入/输出缓冲器具有连接在集成电路上的电源电压和电气系统导体之间的第一多个下拉晶体管，以及连接在电导体和系统参考电压之间的第二多个下拉晶体管。参考电路产生信号以接通第一数量的所述第一多个上拉晶体管和/或第二数量的所述第二多个下拉晶体管，以提供匹配外部传输线路的阻抗的输入/输出缓冲器阻抗将信号发送到可编程输入/输出缓冲器或从可编程输入/输出缓冲器接收信号。

2. 发明授权

US6125421A Independent multichannel memory architecture 失效
标题翻译：独立的多通道内存架构
公开(公告)号：US6125421A
公开(公告)日：2000-09-26
申请号：US73332
申请日：1998-05-06
申请人： Richard Stephen Roy
发明人： Richard Stephen Roy
IPC分类号： G06F12/00 , G06F13/16 , G11C5/06 , G11C7/10
CPC分类号： G11C7/1006 , G11C5/066 , G11C7/1015 , G11C7/1045
摘要： An independent memory architecture is provided which includes a plurality of multi-line channels each capable of carrying either data or address information to a plurality of independent memory clusters. The channels operate independently to access and store data in separate ones of the memory clusters. The independent operation enables faster and more efficient utilization within a memory device over any prior art memory architecture. Each of the clusters have one or more independently addressable memory banks respectively having a plurality of data storage locations organized into respective arrays with each of the storage locations having a distinct column and row address.
摘要翻译：提供独立的存储器架构，其包括多个多行信道，每个多行信道能够将数据或地址信息传送到多个独立存储器簇。信道独立地操作以将数据存储在存储器簇的单独存储器中。独立操作使存储器设备内的任何现有技术的存储架构能够更快更有效地利用。每个簇具有分别具有组织到相应阵列中的多个数据存储位置的一个或多个可独立寻址的存储体，其中每个存储位置具有不同的列和行地址。

3. 发明授权

US5808487A Multi-directional small signal transceiver/repeater 失效
标题翻译：多方向小信号收发器/中继器
公开(公告)号：US5808487A
公开(公告)日：1998-09-15
申请号：US756050
申请日：1996-11-26
申请人： Richard Stephen Roy
发明人： Richard Stephen Roy
IPC分类号： G11C7/10 , H03K19/00
CPC分类号： G11C7/1006
摘要： A signal transfer circuit for enabling rapids transfer of differential electrical signals among multiple signal paths is provided. The circuit comprises first and second pairs of signal transfer terminals, a pair of internal nodes, first and second pairs of isolation devices, a differential signal amplifier, a gain-enhancing cross-coupled pair of devices, and a precharge circuit. The first and second pairs of isolation devices are of a single device type and are coupled between respective ones of the signal transfer terminal pairs and the internal node pair. The isolation devices each have a control terminal for receiving an isolation control signal. The differential signal amplifier circuit is coupled to the internal nodes, and is comprised of complementary device types. The amplifier circuit has a control terminal for receiving an amplifier control signal for enabling the amplifier circuit. The gain-enhancing cross-coupled pair of devices are gated by the internal nodes and drive the transfer terminals directly. The precharge circuit is coupled to the pair of internal nodes and has a control terminal for receiving an internal precharge control signal. A differential signal applied to one of the pair of transfer signal terminals is transferred to the internal nodes for amplification by the differential amplifier circuit, and after which the amplified differential signal on the internal nodes is transferred without inversion to a different pair of transfer signal terminals.
摘要翻译：提供了一种用于在多个信号路径中实现差分电信号的急流传送的信号传送电路。电路包括第一和第二对信号传输终端，一对内部节点，第一和第二对隔离装置，差分信号放大器，增益增强交叉耦合对装置和预充电电路。第一和第二对隔离器件是单一器件类型的，并且耦合在信号传输终端对和内部节点对中的各个之间。隔离装置各自具有用于接收隔离控制信号的控制端子。差分信号放大器电路耦合到内部节点，并且由互补的器件类型组成。放大器电路具有用于接收用于使能放大器电路的放大器控制信号的控制端子。增益交叉耦合对器件由内部节点门控，直接驱动传输终端。预充电电路耦合到一对内部节点，并具有用于接收内部预充电控制信号的控制端子。施加到一对传送信号端子之一的差分信号被传送到内部节点用于由差分放大器电路进行放大，之后在内部节点上放大的差分信号被转换而不反转到不同的一对传输信号端子。

4. 发明授权

US6065092A Independent and cooperative multichannel memory architecture for use with master device 失效
标题翻译：与主设备一起使用的独立和协作的多通道存储器架构
公开(公告)号：US6065092A
公开(公告)日：2000-05-16
申请号：US959280
申请日：1997-10-24
申请人： Richard Stephen Roy
发明人： Richard Stephen Roy
IPC分类号： G06F12/00 , G06F13/16 , G11C5/06 , G11C7/10
CPC分类号： G11C7/1006 , G11C5/066 , G11C7/1015 , G11C7/1045
摘要： An independent and cooperative memory architecture is provided which includes a plurality of multi-line channels each capable of carrying either data or address information to a plurality of independent memory clusters. The channels can either operate independently to access and store data in separate ones of the memory clusters, or cooperatively to access and store data in one of the memory clusters. The independent and cooperative operation enables faster and more efficient utilization within a memory device over any prior art memory architecture. Each of the clusters have one or more independently addressable memory banks respectively having a plurality of data storage locations organized into respective arrays with each of the storage locations having a distinct column and row address. The multi-line channels provide a plurality of distinct operating modes for conducting selected data read and/or write transactions within the clusters.
摘要翻译：提供独立且协作的存储器结构，其包括多个多行信道，每个多行信道能够将数据或地址信息携带到多个独立存储器簇。信道可以独立地操作以将数据存储在存储器簇的单独存储器集群中，或者协同地访问和存储在存储器簇之一中的数据。独立和协作的操作使得能够在任何现有技术的存储器架构内在存储器件内更快更有效地利用。每个簇具有分别具有组织到相应阵列中的多个数据存储位置的一个或多个可独立寻址的存储体，其中每个存储位置具有不同的列和行地址。多行通道提供多个不同的操作模式，用于在集群内进行所选择的数据读取和/或写入事务。

5. 发明授权

US5805873A Phase linking of output clock with master clock in memory architecture 失效
标题翻译：输出时钟与存储器架构中的主时钟的相位链接
公开(公告)号：US5805873A
公开(公告)日：1998-09-08
申请号：US650415
申请日：1996-05-20
申请人： Richard Stephen Roy
发明人： Richard Stephen Roy
IPC分类号： G06F12/00 , G06F13/16 , G11C5/06 , G11C7/10 , G06F1/10
CPC分类号： G11C7/1006 , G11C5/066 , G11C7/1015 , G11C7/1045
摘要： An independent and cooperative memory architecture is provided which includes a plurality of multi-line channels each capable of carrying either data or address information to a plurality of independent memory clusters. The memory architecture includes a slave port for shifting the burden of scheduling and synchronization from a master device to a memory device. By coupling the master device's clock signal to a counter and to an enabler coupled to a FIFO, the slave port makes it possible for the master device to request data from the memory device and to begin clocking out the requested data from the slave port after a fixed number of clock cycles of the master device's clock. The slave port guarantees that data from the memory device is available to the master device following an output access time of the memory device.
摘要翻译：提供独立且协作的存储器结构，其包括多个多行信道，每个多行信道能够将数据或地址信息携带到多个独立存储器簇。存储器架构包括用于将调度和同步的负担从主设备转移到存储设备的从端口。通过将主设备的时钟信号耦合到计数器和耦合到FIFO的启动器，从端口使得主设备可以从存储器设备请求数据并且在从站端口开始时从从端口开始计时主设备时钟的固定时钟周期数。从端口保证在存储器件的输出访问时间之后，来自存储器件的数据可用于主器件。

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