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1. 发明授权

US07308623B2 Integrated circuit and method for testing memory on the integrated circuit 有权
标题翻译：用于集成电路测试存储器的集成电路和方法
公开(公告)号：US07308623B2
公开(公告)日：2007-12-11
申请号：US11076020
申请日：2005-03-10
申请人： Richard Slobodnik , Paul Stanley Hughes , Frank David Frederick , Brandon Michael Backlund
发明人： Richard Slobodnik , Paul Stanley Hughes , Frank David Frederick , Brandon Michael Backlund
IPC分类号： G11C29/00
CPC分类号： G11C29/16 , G11C29/26 , G11C29/48 , G11C2029/0401 , G11C2029/3602
摘要： An integrated circuit and method for testing memory on that integrated circuit includes processing logic operable to perform data processing operations on data, and a number of memory units operable to store data for access by the processing logic. A memory test controller is also provided for executing test events in order to seek to detect any memory defects in the number of memory units. The controller includes a storage operable to store event defining information for each of a plurality of test events forming a sequence of test events to be executed, and an interface which, during a single programming operation, receives the event defining information for each of the plurality of test events and causes that event defining information to be stored in the storage. Event processing logic within the controller is then operable, following the single programming operation, to execute the sequence of test events.
摘要翻译：用于在该集成电路上测试存储器的集成电路和方法包括可操作以对数据执行数据处理操作的处理逻辑，以及可操作以存储用于由处理逻辑访问的数据的多个存储单元。还提供了用于执行测试事件的存储器测试控制器，以便寻求检测存储器单元数量中的任何存储器缺陷。所述控制器包括存储器，用于存储形成要执行的测试事件序列的多个测试事件中的每一个的事件定义信息，以及在单个编程操作期间接收所述多个测试事件中的每一个的事件定义信息的接口的测试事件，并导致将事件定义为存储在存储器中的信息。然后，控制器中的事件处理逻辑可以在单个编程操作之后执行测试事件的顺序。

2. 发明授权

US07434119B2 Method and apparatus for memory self testing 有权
标题翻译：记忆自检的方法和装置
公开(公告)号：US07434119B2
公开(公告)日：2008-10-07
申请号：US11072626
申请日：2005-03-07
申请人： Richard Slobodnik , Frank David Frederick
发明人： Richard Slobodnik , Frank David Frederick
IPC分类号： G11C29/00
CPC分类号： G11C29/18 , G11C2029/1806 , G11C2029/3602
摘要： A memory self-test system is provided comprising a self-test controller operable in self-test mode to generate a sequence of generated memory addresses for performing memory access operations associated with the memory test algorithm having an associated memory cell physical access pattern. A programmable re-mapper is operable to re-map the sequence of generated memory addresses derived from the self-test instruction to a sequence of re-mapped memory addresses. The programmable re-mapper performs this re-mapping in response to programmable mapping selection data. The re-mapping of the generated memory addresses to re-mapped memory addresses ensures that the memory cell accesses performed during execution of the memory self-test are consistent with the associated memory cell physical access pattern regardless of the particular implementation of the memory array.
摘要翻译：提供了一种存储器自检系统，其包括在自检模式下可操作的自检程序，以生成一系列生成的存储器地址，以执行与具有相关联的存储单元物理访问模式的存储器测试算法相关联的存储器访问操作。可编程重新映射器可操作以将从自测试指令导出的生成的存储器地址的序列重新映射到重新映射的存储器地址的序列。可编程重新映射器响应于可编程映射选择数据执行该重映射。将生成的存储器地址重新映射到重新映射的存储器地址确保在执行存储器自检期间执行的存储器单元访问与相关联的存储器单元物理访问模式一致，而不管存储器阵列的特定实现。

3. 发明授权

US07330994B2 Clock control of a multiple clock domain data processor 有权
公开(公告)号：US07330994B2
公开(公告)日：2008-02-12
申请号：US11114240
申请日：2005-04-26
申请人： Frank David Frederick
发明人： Frank David Frederick
IPC分类号： G06F1/04 , G06F11/00
CPC分类号： G01R31/31727
摘要： A processor clock control device operable to control a plurality of clock signals output to a processor, said processor comprising a plurality of domains each clocked by a respective one of said plurality of clock signals, said processor being operable in different modes including a functional mode and a test mode, said processor clock control device comprising: a clock signal input operable to receive a slower reference clock signal or a higher speed operational clock signal; at least two clock signal outputs each operable to output a clock signal to a respective domain of said processor; a mode control signal input operable to receive a mode control signal indicating a mode of operation of said processor; a launch control signal input operable to receive a launch control signal, said launch control signal indicating portions of said processor to be tested; and an initiation signal input operable to receive an initiation signal indicating initiation of a processor test; wherein said processor clock control device is operable: in response to receipt of a test mode signal at said mode control signal input to receive a reference clock at said clock signal input and to output said reference clock at at least one of said plurality of clock signal outputs; and in response to a predetermined launch control signal received at said launch control signal input, said predetermined launch control signal indicating testing of a path between one of said clocked domains clocked by one of said clock signal outputs and one other of said clocked domains clocked by one other of said clock signal outputs, and following receipt of said initiation signal, to independently control said plurality of clock signal outputs such that at least one launch clock pulse is output from said one of said clock signal outputs while said one other of said clock signal outputs is suppressed, and following this to output at least one capture clock pulse from said one other of said clock signal outputs while said one of said plurality of clock signal outputs is suppressed.

4. 发明授权

US06999900B2 Testing memory access signal connections 有权
标题翻译：测试存储器访问信号连接
公开(公告)号：US06999900B2
公开(公告)日：2006-02-14
申请号：US10812309
申请日：2004-03-30
申请人： Teresa Louise McLaurin , Frank David Frederick
发明人： Teresa Louise McLaurin , Frank David Frederick
IPC分类号： G06F19/00
CPC分类号： G06F11/267 , G01R31/31717 , G11C29/02 , G11C29/022 , G11C2029/3202
摘要： In order to test the memory access signal connections between a data processing circuit, such as a processor core 2, and a memory 4, a subset of memory access signal connections 8 are provided with associated scan chain cells 10 so that they may be directly tested. The remainder memory access signal connections 12 which are common to all the expected configurations of the memory 4 are tested by being driven by the processor core 2 itself with data being passed through the memory and captured back within the processor core 2 for checking.
摘要翻译：为了测试数据处理电路（例如处理器核心2）和存储器4之间的存储器访问信号连接，存储器访问信号连接8的子集被提供有相关联的扫描链单元10，使得它们可以被直接测试。存储器4的所有预期配置共同的剩余存储器访问信号连接12被处理器核心2本身驱动，数据被传送通过存储器并被捕获回到处理器核心2中进行检查。

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