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1. 发明申请

US20090050972A1 Strained Semiconductor Device and Method of Making Same 审中-公开
标题翻译：应变半导体器件及其制造方法
公开(公告)号：US20090050972A1
公开(公告)日：2009-02-26
申请号：US11841516
申请日：2007-08-20
申请人： Richard Lindsay , Shyue Seng Tan , Joo-Chan Kim , Jun Jung Kim , Hyung-Yoon Choi , Chung Woh Lai , Johnny Widodo
发明人： Richard Lindsay , Shyue Seng Tan , Joo-Chan Kim , Jun Jung Kim , Hyung-Yoon Choi , Chung Woh Lai , Johnny Widodo
IPC分类号： H01L21/768 , H01L23/48 , H01L21/336 , H01L29/78
CPC分类号： H01L29/7843 , H01L21/28518 , H01L21/76834 , H01L21/76843 , H01L21/76855 , H01L21/823807 , H01L21/823871 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A method of making a semiconductor device is disclosed. A semiconductor body, a gate electrode and source/drain regions are provided. A liner is provided that covers the gate electrode and the source/drain regions. Silicide regions are formed on the semiconductor device by etching a contact hole through the liner.
摘要翻译：公开了制造半导体器件的方法。提供半导体本体，栅极电极和源极/漏极区域。提供覆盖栅极电极和源极/漏极区域的衬垫。通过蚀刻通过衬套的接触孔，在半导体器件上形成硅化物区域。

2. 发明申请

US20080057636A1 Strained semiconductor device and method of making same 审中-公开
标题翻译：应变半导体器件及其制造方法
公开(公告)号：US20080057636A1
公开(公告)日：2008-03-06
申请号：US11521809
申请日：2006-09-15
申请人： Richard Lindsay , Joo-Chan Kim
发明人： Richard Lindsay , Joo-Chan Kim
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L21/823807 , H01L29/7848
摘要： A method of making a semiconductor device is disclosed. A first heavily doped region of a first conductivity type is implanted in a first portion of the semiconductor body and a first upper surface anneal is performed. After performing the first upper surface anneal, a second heavily doped region of a second conductivity type is implanted in a second portion of the semiconductor body. After implanting the second heavily doped region, a second upper surface anneal is performed.
摘要翻译：公开了制造半导体器件的方法。第一导电类型的第一重掺杂区域被注入到半导体本体的第一部分中，并执行第一上表面退火。在执行第一上表面退火之后，将第二导电类型的第二重掺杂区注入半导体本体的第二部分。在注入第二重掺杂区域之后，执行第二上表面退火。

3. 发明授权

US08338887B2 Buried gate transistor 有权
标题翻译：埋栅极晶体管
公开(公告)号：US08338887B2
公开(公告)日：2012-12-25
申请号：US11175835
申请日：2005-07-06
申请人： Richard Lindsay , Matthias Hierlemann
发明人： Richard Lindsay , Matthias Hierlemann
IPC分类号： H01L29/66
CPC分类号： H01L29/42356 , H01L21/26586 , H01L21/28097 , H01L21/28194 , H01L21/823807 , H01L21/823828 , H01L21/823885 , H01L27/088 , H01L27/10876 , H01L29/1083 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/66575 , H01L29/6659 , H01L29/66613 , H01L29/66621
摘要： An embodiment of the invention provides a semiconductor fabrication method. The method comprises forming an isolation region between a first and a second region in a substrate, forming a recess in the substrate surface, and lining the recess with a uniform oxide. Embodiments further include doping a channel region under the bottom recess surface in the first and second regions and depositing a gate electrode material in the recess. Preferred embodiments include forming source/drain regions adjacent the channel region in the first and second regions, preferably after the step of depositing the gate electrode material. Another embodiment of the invention provides a semiconductor device comprising a recess in a surface of the first and second active regions and in the isolation region, and a dielectric layer having a uniform thickness lining the recess.
摘要翻译：本发明的实施例提供半导体制造方法。该方法包括在衬底中的第一和第二区域之间形成隔离区域，在衬底表面中形成凹陷，并且用均匀的氧化物衬里凹部。实施例还包括在第一和第二区域中的底部凹陷表面下方掺杂沟道区域，并且在凹槽中沉积栅电极材料。优选的实施方案包括在第一和第二区域中形成邻近沟道区的源/漏区，优选在沉积栅电极材料的步骤之后。本发明的另一个实施例提供一种半导体器件，其包括在第一和第二有源区域的表面中以及在隔离区域中的凹部，以及在凹部内衬有均匀厚度的介电层。

4. 发明授权

US07785946B2 Integrated circuits and methods of design and manufacture thereof 有权
标题翻译：集成电路及其设计和制造方法
公开(公告)号：US07785946B2
公开(公告)日：2010-08-31
申请号：US11860955
申请日：2007-09-25
申请人： Henning Haffner , Manfred Eller , Richard Lindsay
发明人： Henning Haffner , Manfred Eller , Richard Lindsay
IPC分类号： H01L21/338
CPC分类号： G06F17/5072 , G03F1/00 , G06F2217/12 , H01L21/0334 , H01L21/28123 , H01L21/823425 , H01L21/823437 , H01L27/0207 , H01L27/082 , H01L27/085 , H01L27/088 , H01L29/6659 , H01L29/7833 , Y10T29/41
摘要： Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.
摘要翻译：公开了集成电路及其制造和设计方法。例如，制造方法包括使用第一掩模对形成多个第一和第二特征的栅极材料进行图案化。第一特征形成半导体器件的栅电极，而第二特征是虚拟电极。基于这些虚拟电极的位置，使用第二掩模去除所选择的虚拟电极。该方法的使用提供了更大的灵活性，为不同的目标定制单个设备。

5. 发明申请

US20100117159A1 Strained Semiconductor Device and Method of Making Same 有权
标题翻译：应变半导体器件及其制造方法
公开(公告)号：US20100117159A1
公开(公告)日：2010-05-13
申请号：US12692296
申请日：2010-01-22
申请人： Richard Lindsay
发明人： Richard Lindsay
IPC分类号： H01L29/78
CPC分类号： H01L21/823807 , H01L21/26506 , H01L21/823814 , H01L21/823878 , H01L29/66795 , H01L29/7846 , H01L29/7848 , H01L29/785
摘要： A method of making a semiconductor device is disclosed. An upper surface of a semiconductor body is amorphized and a liner is formed over the amorphized upper surface. The upper surface can then be annealed. A transistor is formed at the upper surface.
摘要翻译：公开了制造半导体器件的方法。半导体本体的上表面非晶化，在非晶化上表面上形成衬垫。然后可以对上表面退火。晶体管形成在上表面。

6. 发明申请

US20070069309A1 Buried well for semiconductor devices 审中-公开
标题翻译：埋在半导体器件上
公开(公告)号：US20070069309A1
公开(公告)日：2007-03-29
申请号：US11235575
申请日：2005-09-26
申请人： Richard Lindsay , Phung Nguyen , Jeong-Hwan Yang
发明人： Richard Lindsay , Phung Nguyen , Jeong-Hwan Yang
IPC分类号： H01L29/76
CPC分类号： H01L29/105 , H01L29/1087
摘要： A substrate having a buried well is provided. The substrate may be formed by implanting ions in a surface well of a first substrate and subsequently forming a semiconductor layer, such as an epitaxial layer, over the surface well. In this manner, the surface well becomes a buried well having a semiconductor layer that is substantially undoped formed thereon. In an embodiment, a transistor is formed on the substrate. Because the epitaxial layer is substantially undoped, the transistor may be formed such that the junction capacitance between the source/drain regions and the underlying region is reduced. If desired, the epitaxial layer, or a portion thereof, may be doped to decrease the resistance between the channel region and the well contact.
摘要翻译：提供具有埋置井的衬底。衬底可以通过在第一衬底的表面阱中注入离子并随后在表面上形成诸如外延层的半导体层来形成。以这种方式，表面阱成为具有基本上未掺杂的半导体层的掩埋阱。在一个实施例中，在衬底上形成晶体管。因为外延层基本上是未掺杂的，所以可以形成晶体管，使得源极/漏极区域与下面的区域之间的结电容减小。如果需要，可以掺杂外延层或其一部分以减小沟道区和阱接触之间的电阻。

7. 发明申请

US20050156091A1 Tiltable mountings for payloads 有权
标题翻译：可倾斜安装用于有效载荷
公开(公告)号：US20050156091A1
公开(公告)日：2005-07-21
申请号：US10507901
申请日：2003-03-20
申请人： Richard Lindsay
发明人： Richard Lindsay
IPC分类号： F16M11/12 , F16F15/28 , F16M11/10 , A47G29/00
CPC分类号： F16F15/28 , F16M11/10 , F16M11/2014 , F16M11/34 , F16M2200/041
摘要： A tiltable mounting as claimed in any of the preceding claims, wherein the lever has a conical shaped roller engaging the cam, the roller being mounted for rotation on the lever about an axis which passes through the pivotal axis of the lever and the conical surface of the roller having a projected apex which coincides with the pivotal axis of the roller to minimise sliding movement at the line of contact of the roller and cam as the roller moves over the cam surface.
摘要翻译： 5.根据前述权利要求中任一项所述的可倾斜安装件，其特征在于，所述杠杆具有接合所述凸轮的圆锥形滚子，所述滚子被安装成绕所述杠杆转动，所述轴线穿过所述杠杆的枢转轴线并且所述圆锥形表面辊具有与辊的枢转轴线重合的突出的顶点，以最小化当辊在凸轮表面上移动时在辊和凸轮的接触线处的滑动运动。

8. 发明申请

US20120074499A1 Integrated Circuits and Methods of Design and Manufacture Thereof 有权
标题翻译：集成电路及其设计和制造方法
公开(公告)号：US20120074499A1
公开(公告)日：2012-03-29
申请号：US13296578
申请日：2011-11-15
申请人： Henning Haffner , Manfred Eller , Richard Lindsay
发明人： Henning Haffner , Manfred Eller , Richard Lindsay
IPC分类号： H01L27/08 , G03F1/38 , G03F1/48 , G06F17/50 , G03F1/00
CPC分类号： G06F17/5072 , G03F1/00 , G06F2217/12 , H01L21/0334 , H01L21/28123 , H01L21/823425 , H01L21/823437 , H01L27/0207 , H01L27/082 , H01L27/085 , H01L27/088 , H01L29/6659 , H01L29/7833 , Y10T29/41
摘要： Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.
摘要翻译：公开了集成电路及其制造和设计方法。例如，制造方法包括使用第一掩模对形成多个第一和第二特征的栅极材料进行图案化。第一特征形成半导体器件的栅电极，而第二特征是虚拟电极。基于这些虚拟电极的位置，使用第二掩模去除所选择的虚拟电极。该方法的使用提供了更大的灵活性，为不同的目标定制单个设备。

9. 发明授权

US08003458B2 Methods of manufacturing a semiconductor device with active regions of different heights 有权
标题翻译：制造具有不同高度的有源区域的半导体器件的方法
公开(公告)号：US08003458B2
公开(公告)日：2011-08-23
申请号：US12710911
申请日：2010-02-23
申请人： Frank Huebinger , Richard Lindsay
发明人： Frank Huebinger , Richard Lindsay
IPC分类号： H01L21/8238
CPC分类号： H01L21/823878 , H01L21/76224 , H01L21/823821 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a first transistor having a first active area, and a second transistor having a second active area. A top surface of the first active area is elevated or recessed with respect to a top surface of the second active area, or a top surface of the first active area is elevated or recessed with respect to a top surface of at least portions of an isolation region proximate the first transistor.
摘要翻译：公开了半导体器件及其制造方法。在一个实施例中，半导体器件包括具有第一有源区的第一晶体管和具有第二有源区的第二晶体管。第一有源区的顶表面相对于第二有源区的顶表面升高或凹入，或者第一有源区的顶表面相对于隔离层的至少部分的顶表面被升高或凹入区域靠近第一晶体管。

10. 发明申请

US20100276759A1 Integrated Circuits and Methods of Design and Manufacture Thereof 有权
标题翻译：集成电路及其设计和制造方法
公开(公告)号：US20100276759A1
公开(公告)日：2010-11-04
申请号：US12839750
申请日：2010-07-20
申请人： Henning Haffner , Manfred Eller , Richard Lindsay
发明人： Henning Haffner , Manfred Eller , Richard Lindsay
IPC分类号： H01L27/088 , H01L27/02 , G06F17/50 , H01L21/64
CPC分类号： G06F17/5072 , G03F1/00 , G06F2217/12 , H01L21/0334 , H01L21/28123 , H01L21/823425 , H01L21/823437 , H01L27/0207 , H01L27/082 , H01L27/085 , H01L27/088 , H01L29/6659 , H01L29/7833 , Y10T29/41
摘要： Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.
摘要翻译：公开了集成电路及其制造和设计方法。例如，制造方法包括使用第一掩模对形成多个第一和第二特征的栅极材料进行图案化。第一特征形成半导体器件的栅电极，而第二特征是虚拟电极。基于这些虚拟电极的位置，使用第二掩模去除所选择的虚拟电极。该方法的使用提供了更大的灵活性，为不同的目标定制单个设备。

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