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1. 发明申请

US20060190552A1 Data retention system with a plurality of access protocols 审中-公开
标题翻译：具有多个访问协议的数据保留系统
公开(公告)号：US20060190552A1
公开(公告)日：2006-08-24
申请号：US11065690
申请日：2005-02-24
申请人： Richard Henze , Padmanabha Venkitakrishnan , Scott Marovich , Pankaj Mehra , Samuel Fineberg
发明人： Richard Henze , Padmanabha Venkitakrishnan , Scott Marovich , Pankaj Mehra , Samuel Fineberg
IPC分类号： G06F15/167
CPC分类号： H04L67/1097 , H04L29/12009 , H04L61/00 , H04L69/18
摘要： A data retention system is described that has a plurality of access protocols. The system comprises a memory store accessible through a virtual address space, a controller communicatively coupled to the memory store, and an interface. The controller is adapted to implement a memory access protocol for accessing at least a first portion of the virtual address space and a secondary storage protocol for accessing at least a second portion of the virtual address space. The interface is communicatively coupled to the controller, and is able to be communicatively coupled to a communications link.
摘要翻译：描述了具有多个访问协议的数据保留系统。该系统包括可通过虚拟地址空间访问的存储器存储器，通信地耦合到存储器存储器的控制器和接口。控制器适于实现用于访问虚拟地址空间的至少第一部分的存储器访问协议和用于访问虚拟地址空间的至少第二部分的辅助存储协议。该接口通信地耦合到控制器，并且能够通信地耦合到通信链路。

2. 发明授权

US06874014B2 Chip multiprocessor with multiple operating systems 有权
标题翻译：具有多个操作系统的片上多处理器
公开(公告)号：US06874014B2
公开(公告)日：2005-03-29
申请号：US09865605
申请日：2001-05-29
申请人： Stephen E. Richardson , Gary Vondran , Stuart Siu , Paul Keltcher , Shankar Venkataraman , Padmanabha Venkitakrishnan , Joseph Ku
发明人： Stephen E. Richardson , Gary Vondran , Stuart Siu , Paul Keltcher , Shankar Venkataraman , Padmanabha Venkitakrishnan , Joseph Ku
IPC分类号： G06F9/50 , G06F15/167 , G06F11/00
CPC分类号： G06F9/5077 , G06F15/167 , Y02D10/22 , Y02D10/36
摘要： Multiple processors are mounted on a single die. The die is connected to a memory storing multiple operating systems or images of multiple operating systems. Each of the processors or a group of one or more of the processors is operable to execute a distinct one of the multiple operating systems. Therefore, resources for a single operating system may be dedicated to one processor or a group of processors. Consequently, a large number of processors mounted on a single die can operate efficiently.
摘要翻译：多个处理器安装在单个管芯上。模具连接到存储多个操作系统或多个操作系统的映像的存储器。每个处理器或一组或多个处理器可操作以执行多个操作系统中不同的一个。因此，用于单个操作系统的资源可以专用于一个处理器或一组处理器。因此，安装在单个管芯上的大量处理器可以有效地工作。

3. 发明授权

US06513145B1 Method for estimating the power consumed in a microprocessor 有权
标题翻译：用于估计微处理器消耗的功率的方法
公开(公告)号：US06513145B1
公开(公告)日：2003-01-28
申请号：US09920416
申请日：2001-07-31
申请人： Padmanabha Venkitakrishnan
发明人： Padmanabha Venkitakrishnan
IPC分类号： G06F1750
CPC分类号： G06F17/5022 , G06F2217/78
摘要： In one embodiment, the present invention provides a method for estimating the maximum power consumed in a microprocessor or other architecture, at an architectural level, prior to implementation. A functional model represents the architecture at a high level of abstraction. In one embodiment, the model is written in SystemC. In one embodiment, power consumption is expressed power weights, derived by reference to architecture technology. In one embodiment, a method of estimating power consumption prior to implementation operates by modeling a benchmark, compiling it into an instruction stream, assigning power weights for each stage of each architectural function, running the model in a maximum power consumption mode, and summarizing the resulting power consumption. In one embodiment, a PERL script compiler is used. In one embodiment, the power weights are calculated corresponding to the characteristic architecture technology. In one embodiment, a power virus program runs the model in the maximum power mode.
摘要翻译：在一个实施例中，本发明提供了一种用于在实施之前估计在架构级别的微处理器或其他架构中消耗的最大功率的方法。功能模型代表了抽象层次上的架构。在一个实施例中，该模型是在SystemC中编写的。在一个实施例中，功率消耗被表示为通过参考架构技术导出的功率权重。在一个实施例中，在实现之前估计功耗的方法通过对基准进行建模，将其编译为指令流，为每个架构功能的每个阶段分配功率权重，以最大功耗模式运行模型来操作，并且总结导致功耗。在一个实施例中，使用PERL脚本编译器。在一个实施例中，对应于特征架构技术计算功率权重。在一个实施例中，电源病毒程序以最大功率模式运行模型。

4. 发明授权

US07003441B2 Method for deriving the benchmark program for estimating the maximum power consumed in a microprocessor 有权
公开(公告)号：US07003441B2
公开(公告)日：2006-02-21
申请号：US09920382
申请日：2001-07-31
申请人： Padmanabha Venkitakrishnan
发明人： Padmanabha Venkitakrishnan
IPC分类号： G06F17/50
CPC分类号： G06F1/32 , G06F1/26
摘要： In one embodiment, for an electronic architecture with a functional constitution performing a number of functions characterized by separate stages performing subfunctions, a method of deriving a benchmark program for estimating the maximum power consumption by modeling a functional model of the architecture, compiling the benchmark program into a corresponding instruction stream, valuating power weights for each stage of each function of each constituent, inserting the power weights, running the model in a maximum power consumption mode, and summarizing power consumption. In one embodiment, the benchmark program is applied by specifying a design analysis to be performed, selecting a function, designating a stages performing that function, removing a set of instruction set architecture instructions corresponding the designated stage, emulating the constituent subfunction corresponding to the stages designated stage, and summarizing. In one embodiment, the model is written in SystemC. In one embodiment, a compiler used is a PERL script.

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