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1. 发明授权

US08164499B1 Shared-array multiple-output digital-to-analog converter 有权
标题翻译：共享阵列多输出数模转换器
公开(公告)号：US08164499B1
公开(公告)日：2012-04-24
申请号：US12813540
申请日：2010-06-11
申请人： Richard Booth , Paulius Mosinskis , Phillip Johnson , David Onimus
发明人： Richard Booth , Paulius Mosinskis , Phillip Johnson , David Onimus
IPC分类号： H03M1/00
CPC分类号： H03M1/662 , H03M1/747
摘要： In an exemplary decision-feedback equalizer (DFE) of a serializer/deserializer (SerDes) receiver, a single current mirror array is shared by multiple current digital-to-analog converter (IDAC) functions. The DFE has an initial amplifier stage that applies an initial coefficient COEFF0 to an input data signal and a number of (e.g., five) additional amplifier stages that apply additional coefficients (e.g., COEFF1-COEFF5) to different delayed versions of the recovered output data stream. The outputs of the initial and multiple additional amplifier stages are summed to generate an equalized data signal that is applied to a clock-and-data recovery (CDR) circuit. Due to certain characteristics of the equalizer function, the multiple additional amplifier stages can be implemented using a single shared current mirror array, which save significant amounts of chip area compared to conventional implementations in which each additional amplifier stage has its own dedicated current mirror array.
摘要翻译：在串行器/解串器（SerDes）接收器的示例性判决反馈均衡器（DFE）中，单个电流镜阵列由多个当前数模转换器（IDAC）功能共享。 DFE具有初始放大器级，其将初始系数COEFF0应用于输入数据信号和将附加系数（例如，COEFF1-COEFF5）应用于恢复的输出数据的不同延迟版本的（例如，五个）附加放大器级流。将初始和多个附加放大器级的输出相加以产生施加到时钟和数据恢复（CDR）电路的均衡数据信号。由于均衡器功能的某些特性，可以使用单个共享电流镜阵列实现多个附加放大器级，与传统实现相比，其保留了大量的芯片面积，其中每个附加放大器级具有其自己的专用电流镜阵列。

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