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1. 发明申请

US20060292765A1 Method for Making a FINFET Including a Superlattice 审中-公开
标题翻译：制造包含超晶格的FINFET的方法
公开(公告)号：US20060292765A1
公开(公告)日：2006-12-28
申请号：US11426976
申请日：2006-06-28
申请人： Richard Blanchard , Kalipatnam Rao , Scott Kreps
发明人： Richard Blanchard , Kalipatnam Rao , Scott Kreps
IPC分类号： H01L21/84 , H01L21/336
CPC分类号： H01L29/1054 , B82Y10/00 , H01L21/823807 , H01L29/1083 , H01L29/151 , H01L29/152 , H01L29/155 , H01L29/66795 , H01L29/7833 , H01L29/785
摘要： A method for making a semiconductor device may include forming at least one fin field-effect transistor (FINFET) comprising a fin, source and drain regions adjacent opposite sides of the fin, and a gate overlying the fin. The fin may include at least one superlattice including a plurality of stacked groups of layers Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
摘要翻译：制造半导体器件的方法可以包括形成至少一个鳍状场效应晶体管（FINFET），其包括与鳍片相对的两侧相邻的翅片，源极和漏极区域以及覆盖鳍片的栅极。翅片可以包括至少一个超晶格，其包括多个层叠的层组。每组层可以包括限定基极半导体部分的多个堆叠的基底半导体单层，以及约束在相邻的晶体的晶格内的至少一个非半导体单层基极半导体部分。

2. 发明申请

US20060292889A1 FINFET Including a Superlattice 有权
标题翻译： FINFET包括超晶格
公开(公告)号：US20060292889A1
公开(公告)日：2006-12-28
申请号：US11426969
申请日：2006-06-28
申请人： Richard Blanchard , Kalipatnam Rao , Scott Kreps
发明人： Richard Blanchard , Kalipatnam Rao , Scott Kreps
IPC分类号： H01L21/31
CPC分类号： H01L29/151 , B82Y10/00 , H01L29/1054 , H01L29/1083 , H01L29/7833
摘要： A semiconductor device may include at least one fin field-effect transistor (FINFET) comprising a fin, source and drain regions adjacent opposite ends of the fin, and a gate overlying the fin. The fin may include at least one superlattice including a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
摘要翻译：半导体器件可以包括至少一个鳍状场效应晶体管（FINFET），其包括与鳍片的相对端相邻的翅片，源极和漏极区域以及覆盖鳍片的栅极。翅片可以包括至少一个超晶格，其包括多个堆叠的层组。每组层可以包括限定基底半导体部分的多个层叠的基底半导体单层，以及约束在相邻的基底半导体部分的晶格内的至少一个非半导体单层。

3. 发明申请

US20060019454A1 Method for making a semiconductor device comprising a superlattice dielectric interface layer 有权
标题翻译：制造包括超晶格介质界面层的半导体器件的方法
公开(公告)号：US20060019454A1
公开(公告)日：2006-01-26
申请号：US11136747
申请日：2005-05-25
申请人： Robert Mears , Marek Hytha , Scott Kreps , Robert Stephenson , Jean Augustin Yiptong , Ilija Dukovski , Kalipatnam Rao , Samed Halilov , Xiangyang Huang
发明人： Robert Mears , Marek Hytha , Scott Kreps , Robert Stephenson , Jean Augustin Yiptong , Ilija Dukovski , Kalipatnam Rao , Samed Halilov , Xiangyang Huang
IPC分类号： H01L21/336 , H01L21/28 , H01L21/20
CPC分类号： B82Y10/00 , H01L21/823807 , H01L29/1054 , H01L29/152 , H01L29/155 , H01L29/513 , H01L29/7833
摘要： A method for making a semiconductor device may include forming a superlattice comprising a plurality of stacked groups of layers adjacent a substrate. Each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a high-K dielectric layer on the electrode layer, and forming an electrode layer on the high-K dielectric layer and opposite the superlattice.
摘要翻译：制造半导体器件的方法可以包括形成包含与衬底相邻的多个堆叠层组的超晶格。超晶格的每组层可以包括限定基极半导体部分的多个层叠的基底半导体单层和限制在相邻的基极半导体部分的晶格内的至少一个非半导体单层。该方法还可以包括在电极层上形成高K电介质层，并在高K电介质层上形成与超晶格相对的电极层。

4. 发明申请

US20060243964A1 METHOD FOR MAKING A SEMICONDUCTOR DEVICE HAVING A SEMICONDUCTOR-ON-INSULATOR CONFIGURATION AND A SUPERLATTICE 审中-公开
标题翻译：制造具有半导体绝缘体构造和超导体的半导体器件的方法
公开(公告)号：US20060243964A1
公开(公告)日：2006-11-02
申请号：US11381850
申请日：2006-05-05
申请人： Scott Kreps , Kalipatnam Rao
发明人： Scott Kreps , Kalipatnam Rao
IPC分类号： H01L29/06
CPC分类号： H01L29/155 , H01L29/1054 , H01L29/40114 , H01L29/66825 , H01L29/7881
摘要： A method for making a semiconductor device may include forming an insulating layer adjacent a substrate, forming a superlattice adjacent a semiconductor layer, and positioning the semiconductor layer adjacent a face of the insulating layer opposite the substrate. The method may further include forming a gate overlying the superlattice, and forming source and drain regions on the semiconductor layer so that the superlattice extends therebetween to define a channel. The superlattice may include a plurality of stacked groups of layers with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. The energy band-modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
摘要翻译：制造半导体器件的方法可以包括在衬底附近形成绝缘层，在半导体层附近形成超晶格，并且将半导体层定位在与衬底相对的绝缘层的表面附近。该方法还可以包括形成覆盖超晶格的栅极，以及在半导体层上形成源极和漏极区域，使得超晶格在其间延伸以限定沟道。超晶格可以包括多个堆叠的层组，其中每组层包括限定基极半导体部分和其上的能带修饰层的多个层叠的基底半导体单层。能带修饰层可以包括约束在相邻的基底半导体部分的晶格内的至少一个非半导体单层。

5. 发明申请

US20060261327A1 SEMICONDUCTOR DEVICE HAVING A SEMICONDUCTOR-ON-INSULATOR CONFIGURATION AND A SUPERLATTICE 有权
标题翻译：具有半导体绝缘体构造和超导体的半导体器件
公开(公告)号：US20060261327A1
公开(公告)日：2006-11-23
申请号：US11381835
申请日：2006-05-05
申请人： Scott Kreps , Kalipatnam Rao
发明人： Scott Kreps , Kalipatnam Rao
IPC分类号： H01L29/06
CPC分类号： H01L21/28273 , H01L29/1054 , H01L29/155 , H01L29/665 , H01L29/66636 , H01L29/66825 , H01L29/78696 , H01L29/7881
摘要： A semiconductor device may include a substrate, an insulating layer adjacent the substrate, and a semiconductor layer adjacent a face of the insulating layer opposite the substrate. The device may further include source and drain regions on the semiconductor layer, a superlattice adjacent the semiconductor layer and extending between the source and drain regions to define a channel, and a gate overlying the superlattice. The superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. The energy band-modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
摘要翻译：半导体器件可以包括衬底，与衬底相邻的绝缘层，以及邻近与衬底相对的绝缘层的表面的半导体层。器件还可以包括半导体层上的源极和漏极区域，邻近半导体层并且在源极和漏极区域之间延伸以限定沟道的超晶格和覆盖超晶格的栅极。超晶格可以包括多个堆叠的层组，其中每组层包括限定基底半导体部分和其上的能带修饰层的多个层叠的基底半导体单层。能带修饰层可以包括约束在相邻的基底半导体部分的晶格内的至少一个非半导体单层。

6. 发明申请

US20060011905A1 Semiconductor device comprising a superlattice dielectric interface layer 审中-公开
标题翻译：半导体器件包括超晶格介质界面层
公开(公告)号：US20060011905A1
公开(公告)日：2006-01-19
申请号：US11136881
申请日：2005-05-25
申请人： Robert Mears , Marek Hytha , Scott Kreps , Robert Stephenson , Jean Augustin Chan yiptong , Ilija Dukovski , Kalipatnam Rao , Samed Halilov , Xiangyang Huang
发明人： Robert Mears , Marek Hytha , Scott Kreps , Robert Stephenson , Jean Augustin Chan yiptong , Ilija Dukovski , Kalipatnam Rao , Samed Halilov , Xiangyang Huang
IPC分类号： H01L29/06
CPC分类号： H01L29/152 , B82Y10/00 , H01L21/823807 , H01L29/1054 , H01L29/155 , H01L29/51 , H01L29/513 , H01L29/517 , H01L29/7833
摘要： A semiconductor device may include a semiconductor substrate and at least one active device adjacent the semiconductor substrate. The at least one active device may include an electrode layer, a high-K dielectric layer underlying the electrode layer and in contact therewith, and a superlattice underlying the high-K dielectric layer opposite the electrode layer and in contact with the high-K dielectric layer. The superlattice may include a plurality of stacked groups of layers. Each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
摘要翻译：半导体器件可以包括半导体衬底和邻近半导体衬底的至少一个有源器件。所述至少一个有源器件可包括电极层，位于电极层下方并与其接触的高K电介质层，以及位于与电极层相对的高K电介质层下方并与高K电介质接触的超晶格层。超晶格可以包括多个堆叠的层组。超晶格的每组层可以包括限定基极半导体部分的多个堆叠的基底半导体单层和限制在相邻的基极半导体部分的晶格内的至少一个非半导体单层。

7. 发明申请

US20060263980A1 METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING A FLOATING GATE MEMORY CELL WITH A SUPERLATTICE CHANNEL 审中-公开
标题翻译：用于制造具有超级通道的浮动门存储器单元的半导体器件的方法
公开(公告)号：US20060263980A1
公开(公告)日：2006-11-23
申请号：US11381794
申请日：2006-05-05
申请人： Scott Kreps , Kalipatnam Rao
发明人： Scott Kreps , Kalipatnam Rao
IPC分类号： H01L21/336
CPC分类号： H01L29/7881 , H01L29/1054 , H01L29/155 , H01L29/40114 , H01L29/66825
摘要： A method for making a semiconductor device may include providing a semiconductor substrate and forming at least one non-volatile memory cell. Spaced apart source and drain regions may be formed, and a superlattice channel may be formed between the source and drain regions. The superlattice channel may include a plurality of stacked groups of layers on the substrate between the source and drain regions. Each group of layers of the superlattice channel may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. The energy band-modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A floating gate may be formed adjacent the superlattice channel, and a control gate may be formed adjacent the floating gate.
摘要翻译：制造半导体器件的方法可以包括提供半导体衬底并形成至少一个非易失性存储单元。可以形成间隔开的源极和漏极区，并且可以在源极和漏极区之间形成超晶格沟道。超晶格沟道可以包括在源极和漏极区域之间的衬底上的多个堆叠层组。超晶格通道的每组层可以包括在其上限定基极半导体部分和能带修饰层的多个层叠的基底半导体单层。能带修饰层可以包括约束在相邻的基底半导体部分的晶格内的至少一个非半导体单层。可以在超晶格通道附近形成浮置栅极，并且可以在浮置栅极附近形成控制栅极。

8. 发明申请

US20060243963A1 SEMICONDUCTOR DEVICE INCLUDING A FLOATING GATE MEMORY CELL WITH A SUPERLATTICE CHANNEL 有权
标题翻译：具有超级通道的浮动门存储单元的半导体器件
公开(公告)号：US20060243963A1
公开(公告)日：2006-11-02
申请号：US11381787
申请日：2006-05-05
申请人： Scott Kreps , Kalipatnam Rao
发明人： Scott Kreps , Kalipatnam Rao
IPC分类号： H01L29/06
CPC分类号： H01L21/28273 , H01L29/1054 , H01L29/155 , H01L29/66825 , H01L29/7881
摘要： A semiconductor device may include a semiconductor substrate and at least one non-volatile memory cell. The at least one memory cell may include spaced apart source and drain regions, and a superlattice channel including a plurality of stacked groups of layers on the semiconductor substrate between the source and drain regions. Each group of layers of the superlattice channel may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon, which may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A floating gate may be adjacent the superlattice channel, and a control gate may be adjacent the second gate insulating layer.
摘要翻译：半导体器件可以包括半导体衬底和至少一个非易失性存储单元。所述至少一个存储单元可以包括间隔开的源极和漏极区域，以及在所述源极区域和漏极区域之间的所述半导体衬底上包括多个堆叠层组的超晶格沟道。超晶格通道的每组层可以包括限定基底半导体部分和其上的能带修饰层的多个堆叠的基底半导体单层，其可以包括约束在相邻的基极半导体的晶格内的至少一个非半导体单层部分。浮置栅极可以与超晶格沟道相邻，并且控制栅极可以与第二栅极绝缘层相邻。

9. 发明申请

US20050173696A1 Method for making a semiconductor device including a MOSFET having a band-engineered superlattice with a semiconductor cap layer providing a channel 有权
标题翻译：制造半导体器件的方法，该半导体器件包括具有带状工程超晶格的MOSFET，其具有提供沟道的半导体盖层
公开(公告)号：US20050173696A1
公开(公告)日：2005-08-11
申请号：US11042272
申请日：2005-01-25
申请人： Robert Mears , Jean Augustin Chan Yiptong , Marek Hytha , Scott Kreps , Ilija Dukovski
发明人： Robert Mears , Jean Augustin Chan Yiptong , Marek Hytha , Scott Kreps , Ilija Dukovski
IPC分类号： H01L21/8238 , H01L29/10 , H01L29/15 , H01L29/78 , H01L29/06
CPC分类号： H01L29/1054 , H01L21/823807 , H01L29/155 , H01L29/7833
摘要： A method for making a semiconductor device may include providing a substrate, and forming at least one MOSFET adjacent the substrate by forming a superlattice including a plurality of stacked groups of layers and a semiconductor cap layer on an uppermost group of layers. Each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming source, drain, and gate regions defining a channel through at least a portion of the semiconductor cap layer.
摘要翻译：制造半导体器件的方法可以包括提供衬底，以及通过在最上层组上形成包括多层堆叠层和半导体帽层的超晶格，形成与衬底相邻的至少一个MOSFET。超晶格的每组层可以包括限定基极半导体部分的多个堆叠的基底半导体单层和限制在相邻的基极半导体部分的晶格内的至少一个非半导体单层。该方法还可以包括形成通过半导体盖层的至少一部分限定沟道的源极，漏极和栅极区域。

10. 发明申请

US20050118767A1 Method for making semiconductor device comprising a superlattice with upper portions extending above adjacent upper portions of source and drain regions 有权
标题翻译：一种用于制造半导体器件的方法，该半导体器件包括超晶格，上部部分在源极和漏极区域的相邻上部之上延伸
公开(公告)号：US20050118767A1
公开(公告)日：2005-06-02
申请号：US10940594
申请日：2004-09-14
申请人： Scott Kreps
发明人： Scott Kreps
IPC分类号： H01L21/8238 , H01L29/10 , H01L29/15 , H01L29/78 , H01L21/336
CPC分类号： H01L29/1054 , H01L21/823807 , H01L29/155 , H01L29/7833
摘要： A method for making a semiconductor device may include providing a semiconductor substrate and forming at least one MOSFET by forming spaced apart source and drain regions and a superlattice on the substrate so that the superlattice is between the source and drain regions. The superlattice may include a plurality of stacked groups of layers. The superlattice may have upper portions extending above adjacent upper portions of the source and drain regions, and lower portions contacting the source and drain regions so that a channel is defined in lower portions of the superlattice. Each group of layers of the superlattice may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon. The energy-band modifying layer may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor. The method may further include forming a gate overlying the superlattice.
摘要翻译：制造半导体器件的方法可以包括提供半导体衬底并且通过在衬底上形成间隔开的源极和漏极区域和超晶格来形成至少一个MOSFET，使得超晶格位于源极和漏极区域之间。超晶格可以包括多个堆叠的层组。超晶格可以具有在源极和漏极区域的相邻上部之上延伸的上部，以及接触源极和漏极区域的下部，使得在超晶格的下部限定沟道。超晶格的每组层可以包括在其上限定基极半导体部分和能带改性层的多个堆叠的基底半导体单层。能带修改层可以包括约束在相邻基极半导体的晶格内的至少一个非半导体单层。该方法还可以包括形成覆盖超晶格的栅极。

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