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1. 发明申请

US20070140035A1 Apparatus and Method for Pipelined Memory Operations 有权
标题翻译：流水线存储器操作的装置和方法
公开(公告)号：US20070140035A1
公开(公告)日：2007-06-21
申请号：US11675054
申请日：2007-02-14
申请人： Richard Barth , Ely Tsern , Mark Horowitz , Donald Stark , Craig Hampel , Frederick Ware , John Dillon , Nancy Dillon
发明人： Richard Barth , Ely Tsern , Mark Horowitz , Donald Stark , Craig Hampel , Frederick Ware , John Dillon , Nancy Dillon
IPC分类号： G11C8/00
CPC分类号： G11C7/1006 , G06F13/1615 , G11C7/10 , G11C7/1039 , G11C8/12 , G11C11/4076
摘要： A semiconductor memory device has a memory core that includes at least eight banks of dynamic random access storage cells and an internal data bus coupled to the memory core. The internal data bus receives a plurality of data bits from a selected bank of the memory core. The semiconductor memory device further comprises a first interface to receive a read command from external to the semiconductor memory device and a second interface to output first and second subsets of the plurality of data bits. The first subset is output during a first phase of an external clock signal and the second subset is output during a second phase of the external clock signal. The first phase includes a first edge transition and the second phase includes a second edge transition. The second edge transition is an opposite edge transition with respect to the first edge transition.
摘要翻译：半导体存储器件具有包括至少八个动态随机存取存储单元组和耦合到存储器核的内部数据总线的存储器核心。内部数据总线从存储器核心的选定组接收多个数据位。半导体存储器件还包括从外部接收半导体存储器件的读取命令的第一接口和用于输出多个数据位的第一和第二子集的第二接口。在外部时钟信号的第一阶段期间输出第一子集，并且在外部时钟信号的第二阶段期间输出第二子集。第一阶段包括第一边缘转变，第二阶段包括第二边缘过渡。第二边缘转变是相对于第一边缘转变的相反边缘转变。

2. 发明申请

US20060059299A1 Apparatus and method for pipelined memory operations 有权
公开(公告)号：US20060059299A1
公开(公告)日：2006-03-16
申请号：US11270251
申请日：2005-11-08
申请人： Richard Barth , Ely Tsern , Mark Horowitz , Donald Stark , Craig Hampel , Frederick Ware , John Dillon , Nancy Dillon
发明人： Richard Barth , Ely Tsern , Mark Horowitz , Donald Stark , Craig Hampel , Frederick Ware , John Dillon , Nancy Dillon
IPC分类号： G06F12/00
CPC分类号： G11C7/1006 , G06F13/1615 , G11C7/10 , G11C7/1039 , G11C8/12 , G11C11/4076
摘要： A memory device has interface circuitry and a memory core which make up the stages of a pipeline, each stage being a step in a universal sequence associated with the memory core. The memory device has a plurality of operation units such as precharge, sense, read and write, which handle the primitive operations of the memory core to which the operation units are coupled. The memory device further includes a plurality of transport units configured to obtain information from external connections specifying an operation for one of the operation units and to transfer data between the memory core and the external connections. The transport units operate concurrently with the operation units as added stages to the pipeline, thereby creating a memory device which operates at high throughput and with low service times under the memory reference stream of common applications.

3. 发明申请

US20050066114A1 Protocol for communication with dynamic memory 有权
标题翻译：与动态内存进行通信的协议
公开(公告)号：US20050066114A1
公开(公告)日：2005-03-24
申请号：US10966767
申请日：2004-10-15
申请人： Richard Barth , Frederick Ware , John Dillon , Donald Stark , Craig Hampel , Matthew Griffin
发明人： Richard Barth , Frederick Ware , John Dillon , Donald Stark , Craig Hampel , Matthew Griffin
IPC分类号： G06F13/16 , G11C5/06 , G11C7/10 , G11C7/22 , G11C8/12 , G06F12/00
CPC分类号： G11C7/1078 , G06F13/161 , G11C5/066 , G11C7/10 , G11C7/1072 , G11C7/109 , G11C7/22 , G11C8/12 , G11C11/4076 , G11C11/4096
摘要： A system and method for performing data transfers within a computer system is provided. The system includes a controller configured to dynamically adjust the interleave of the communications required to perform a series of data transfer operations to maximize utilization of the channel over which the communications are to be perform ed. The controller is able to vary the time interval between the transmission of control information that requests a data transfer and the performance of the data transfer by signaling the beginning of the data transfer with a strobe signal sent separate from the control information. The controller is able to defer the determination of how much data will be transferred in the operation by initiating the termination of a data transfer with a termination signal. The method provides a technique for distinguishing between identical control signals that are carried on the same line. The system includes a memory device with control circuitry that allows no more than one memory bank powered by any given power supply line to perform sense or precharge operations.
摘要翻译：提供了一种用于在计算机系统内执行数据传输的系统和方法。该系统包括控制器，其被配置为动态地调整执行一系列数据传送操作所需的通信的交错，以最大限度地利用要进行通信的信道的利用。控制器能够通过用与控制信息分开发送的选通信号通过信令数据传送的开始来改变请求数据传送的控制信息的传输与数据传送的执行之间的时间间隔。控制器能够通过启动具有终止信号的数据传送的终止来推迟在操作中传送多少数据的确定。该方法提供了用于区分同一行上承载的相同控制信号的技术。该系统包括具有控制电路的存储器件，该控制电路允许不超过一个由任何给定电源线供电的存储体进行感测或预充电操作。

4. 发明申请

US20080043546A1 Method of Controlling A Memory Device Having a Memory Core 审中-公开
标题翻译：具有内存核心的存储器件的控制方法
公开(公告)号：US20080043546A1
公开(公告)日：2008-02-21
申请号：US11876567
申请日：2007-10-22
申请人： Richard Barth , Frederick Ware , John Dillon , Donald Stark , Craig Hampel , Matthew Griffin
发明人： Richard Barth , Frederick Ware , John Dillon , Donald Stark , Craig Hampel , Matthew Griffin
IPC分类号： G11C7/00
CPC分类号： G11C7/1078 , G06F13/161 , G11C5/066 , G11C7/10 , G11C7/1072 , G11C7/109 , G11C7/22 , G11C8/12 , G11C11/4076 , G11C11/4096
摘要： Method embodiments including providing control information to a memory device is provided. The control information includes a first code which specifies that a write operation be initiated in the memory device. A signal is provided that indicates when the memory device is to begin sampling write data that is stored in the memory core during the write operation. A first bit of the write data is provided to the memory device during an even phase of a clock signal. A second bit of the write data is provided to the memory device during an odd phase of the clock signal.
摘要翻译：提供了包括向存储器件提供控制信息的方法实施例。控制信息包括指定在存储器件中启动写操作的第一代码。提供了一个信号，指示在写入操作期间存储器件何时开始对存储在存储器核心中的写入数据进行采样。在时钟信号的偶数阶段期间，写入数据的第一位被提供给存储器件。在时钟信号的奇数阶段期间，写数据的第二位被提供给存储器件。

5. 发明申请

US20050154817A1 Method of operation and controlling a memory device 审中-公开
标题翻译：操作和控制存储器件的方法
公开(公告)号：US20050154817A1
公开(公告)日：2005-07-14
申请号：US11030382
申请日：2005-01-06
申请人： Richard Barth , Ely Tsern , Craig Hampel , Frederick Ware , Todd Bystrom , Bradley May , Paul Davis
发明人： Richard Barth , Ely Tsern , Craig Hampel , Frederick Ware , Todd Bystrom , Bradley May , Paul Davis
IPC分类号： G06F12/00 , G06F13/16 , G06F13/42 , G11C7/10 , G11C7/20 , G11C11/4072 , G11C11/4074 , G11C11/4076
CPC分类号： G11C7/1072 , G06F1/3225 , G06F13/1689 , G06F13/1694 , G06F13/4239 , G11C7/20 , G11C8/12 , G11C11/4072 , G11C11/4074 , G11C11/4076 , G11C2207/2227 , G11C2207/2254 , Y02D10/151
摘要： A method of operation of a memory device and system includes receiving a first and second value in embodiments. The first value is representative of a number of clock cycles of a clock signal that elapse between latching a column address and an access of data sensed from a row of memory cells in a memory array. A location of the data is based on the column address. The second value is representative of a number of clock cycles of the clock signal that elapse between the access of data from the memory array and outputting the data. The first and second values are received during an initialization sequence. Information in units of time that represents first and second timing parameters that pertains to the memory device is read from a storage location. The information that represents the first and second timing parameters are then converted from units of time to units of clock cycles to derive the first and second values.
摘要翻译：存储器件和系统的操作方法包括在实施例中接收第一和第二值。第一个值表示在锁存列地址和从存储器阵列中的一行存储器单元传感的数据的访问之间经过的时钟信号的多个时钟周期。数据的位置基于列地址。第二个值表示从存储器阵列访问数据并输出数据之间经过的时钟信号的数个时钟周期。在初始化序列期间接收第一和第二值。从存储位置读取表示与存储器件相关的第一和第二定时参数的以时间为单位的信息。然后将表示第一和第二定时参数的信息从时间单位从时钟周期的单位转换为导出第一和第二值。

6. 发明申请

US20050216654A1 System and module including a memory device having a power down mode 有权
标题翻译：系统和模块包括具有断电模式的存储器件
公开(公告)号：US20050216654A1
公开(公告)日：2005-09-29
申请号：US11137469
申请日：2005-05-25
申请人： Richard Barth , Ely Tsern , Craig Hampel , Frederick Ware , Todd Bystrom , Bradley May , Paul Davis
发明人： Richard Barth , Ely Tsern , Craig Hampel , Frederick Ware , Todd Bystrom , Bradley May , Paul Davis
IPC分类号： G06F12/00 , G06F13/16 , G06F13/42 , G11C7/10 , G11C7/20 , G11C11/4072 , G11C11/4074 , G11C11/4076
CPC分类号： G11C7/1072 , G06F1/3225 , G06F13/1689 , G06F13/1694 , G06F13/4239 , G11C7/20 , G11C8/12 , G11C11/4072 , G11C11/4074 , G11C11/4076 , G11C2207/2227 , G11C2207/2254 , Y02D10/151
摘要： A memory module comprises a memory device including a memory array to store data. An interface receives an instruction to exit a power down mode. A register stores a value representative of a period of time to elapse between exiting from the power down mode and a time at which the memory device is capable of receiving a command to access the data. A storage device stores a plurality of parameter information that pertains to the memory device. The value is based on at least a first parameter information of the plurality of parameter information.
摘要翻译：存储器模块包括存储设备，该存储器设备包括存储数据以存储数据。接口接收退出掉电模式的指令。寄存器存储代表从断电模式退出的时间段与存储器装置能够接收访问数据的命令的时间之间的值。存储装置存储与存储装置有关的多个参数信息。该值基于多个参数信息的至少第一参数信息。

7. 发明申请

US20050237851A1 Asynchronous, high-bandwidth memory component using calibrated timing elements 有权
标题翻译：异步高带宽内存组件使用校准的时序元素
公开(公告)号：US20050237851A1
公开(公告)日：2005-10-27
申请号：US11165797
申请日：2005-06-24
申请人： Frederick Ware , Ely Tsern , Craig Hampel , Donald Stark
发明人： Frederick Ware , Ely Tsern , Craig Hampel , Donald Stark
IPC分类号： G11C7/10 , G11C8/00 , G11C29/02
CPC分类号： G11C7/1051 , G11C7/04 , G11C7/1039 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C7/22 , G11C29/02 , G11C29/028 , G11C29/50012 , G11C2207/2254
摘要： Disclosed herein are embodiments of an asynchronous memory device that use internal delay elements to enable memory access pipelining. In one embodiment, the delay elements are responsive to an input load control signal, and are calibrated with reference to periodically received timing pulses. Different numbers of the delay elements are configured to produce different asynchronous delays and to strobe sequential pipeline elements of the memory device.
摘要翻译：这里公开了使用内部延迟元件来启用存储器访问流水线的异步存储器件的实施例。在一个实施例中，延迟元件响应于输入负载控制信号，并且参考周期性接收的定时脉冲进行校准。不同数量的延迟元件被配置为产生不同的异步延迟并选择存储器件的顺序流水线元件。

8. 发明申请

US20050193183A1 Method and apparatus for initializing dynamic random access memory (DRAM) devices 审中-公开
标题翻译：用于初始化动态随机存取存储器（DRAM）设备的方法和装置
公开(公告)号：US20050193183A1
公开(公告)日：2005-09-01
申请号：US11119319
申请日：2005-04-29
申请人： Richard Barth , Ely Tsern , Craig Hampel , Frederick Ware , Todd Bystrom , Bradley May , Paul Davis
发明人： Richard Barth , Ely Tsern , Craig Hampel , Frederick Ware , Todd Bystrom , Bradley May , Paul Davis
IPC分类号： G06F12/00 , G06F13/16 , G06F13/42 , G11C7/10 , G11C7/20 , G11C11/4072 , G11C11/4074 , G11C11/4076 , G06F1/04
CPC分类号： G11C7/1072 , G06F1/3225 , G06F13/1689 , G06F13/1694 , G06F13/4239 , G11C7/20 , G11C8/12 , G11C11/4072 , G11C11/4074 , G11C11/4076 , G11C2207/2227 , G11C2207/2254 , Y02D10/151
摘要： A memory module comprises a random access memory device having a memory array. The random access memory device includes a first register to store a first value that is representative of a number of clock cycles of a clock signal to elapse between latching a column address and an access of data sensed from a row of memory cells in the memory array, wherein a location of the data is based on the column address. A second register stores a second value that is representative of a number of clock cycles of the clock signal to elapse between the access of data from the memory array and outputting the data. A storage device stores a plurality of parameter information that pertains to the random access memory device. The first value and the second value is based on at least a first parameter information of the plurality of parameter information.
摘要翻译：存储器模块包括具有存储器阵列的随机存取存储器件。随机存取存储器件包括第一寄存器，用于存储表示在锁存列地址和从存储器阵列中的一行存储器单元传感的数据的访问之间经过的时钟信号的时钟周期数的第一值，其中所述数据的位置基于所述列地址。第二寄存器存储表示在从存储器阵列访问数据并输出数据之间经过的时钟信号的时钟周期数的第二值。存储装置存储与随机存取存储装置有关的多个参数信息。第一值和第二值基于多个参数信息的至少第一参数信息。

9. 发明申请

US20050154853A1 Memory device and method of operation of a memory device 审中-公开
标题翻译：存储器件和存储器件的操作方法
公开(公告)号：US20050154853A1
公开(公告)日：2005-07-14
申请号：US11030231
申请日：2005-01-06
申请人： Richard Barth , Ely Tsern , Craig Hampel , Frederick Ware , Todd Bystrom , Bradley May , Paul Davis
发明人： Richard Barth , Ely Tsern , Craig Hampel , Frederick Ware , Todd Bystrom , Bradley May , Paul Davis
IPC分类号： G06F12/00 , G06F13/16 , G06F13/42 , G11C7/10 , G11C7/20 , G11C11/4072 , G11C11/4074 , G11C11/4076
CPC分类号： G11C7/1072 , G06F1/3225 , G06F13/1689 , G06F13/1694 , G06F13/4239 , G11C7/20 , G11C8/12 , G11C11/4072 , G11C11/4074 , G11C11/4076 , G11C2207/2227 , G11C2207/2254 , Y02D10/151
摘要： A method of operation of a memory device and a memory device having registers to store values representing a number of clock cycles to access and output data is provided in embodiments. Data is sensed from an array of memory cells using a plurality of sense amplifiers. A column address that identifies data sensed is latched using the plurality of sense amplifiers. The data is accessed, based on the column address, after a first number of clock cycles of a clock signal have elapsed after latching the column address. The first number of clock cycles is represented by a first value stored in a first register on the memory device. The data is output after a second number of clock cycles have elapsed after accessing the data from the array of memory cells. The second number of clock cycles is represented by a second value stored in a second register on the memory device. A column decoder driving a column select line based on the column address accesses the data.
摘要翻译：在实施例中提供了一种存储器件和存储器件的操作方法，该存储器件具有用于存储表示多个时钟周期以访问和输出数据的值的寄存器。使用多个读出放大器从存储器单元阵列感测数据。使用多个读出放大器来锁存识别感测数据的列地址。在锁存列地址后经过时钟信号的第一个时钟周期之后，基于列地址访问数据。第一数量的时钟周期由存储在存储器件上的第一寄存器中的第一值表示。在从存储单元阵列访问数据之后经过了第二个时钟周期数之后，数据被输出。第二数量的时钟周期由存储在存储器件中的第二寄存器中的第二值表示。基于列地址驱动列选择行的列解码器访问数据。

10. 发明申请

US20050235130A1 System for a memory device having a power down mode and method 有权
标题翻译：具有断电模式和方法的存储器件的系统
公开(公告)号：US20050235130A1
公开(公告)日：2005-10-20
申请号：US11151791
申请日：2005-06-14
申请人： Richard Barth , Ely Tsern , Craig Hampel , Frederick Ware , Todd Bystrom , Bradley May , Paul Davis
发明人： Richard Barth , Ely Tsern , Craig Hampel , Frederick Ware , Todd Bystrom , Bradley May , Paul Davis
IPC分类号： G06F12/00 , G06F13/16 , G06F13/42 , G11C7/10 , G11C7/20 , G11C11/4072 , G11C11/4074 , G11C11/4076
CPC分类号： G11C7/1072 , G06F1/3225 , G06F13/1689 , G06F13/1694 , G06F13/4239 , G11C7/20 , G11C8/12 , G11C11/4072 , G11C11/4074 , G11C11/4076 , G11C2207/2227 , G11C2207/2254 , Y02D10/151
摘要： A system comprising a storage location to store information representing a timing parameter pertaining to a random access memory device. An integrated circuit device generates a value that is representative of a period of time that elapses between the random access memory device exiting from a power down mode and a time at which the random access memory device is capable of receiving a command. The integrated circuit device generates the value from the information representing the timing parameter pertaining to the random access memory device.
摘要翻译：一种系统，包括存储位置以存储表示随机存取存储器件的定时参数的信息。集成电路装置生成代表在从断电模式退出的随机存取存储装置与随机存取存储装置能够接收指令的时间之间经过的时间段的值。集成电路装置根据表示随机存取存储装置的定时参数的信息生成该值。

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