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    • 4. 发明授权
    • Systems and methods for data processing including pre-equalizer noise suppression
    • 用于数据处理的系统和方法,包括预均衡器噪声抑制
    • US08731115B2
    • 2014-05-20
    • US13415326
    • 2012-03-08
    • Shaohua YangJin Lu
    • Shaohua YangJin Lu
    • H04L27/06H03K5/159
    • G11B20/10046G11B20/10379G11B20/1816G11B2020/1287G11B2020/183G11B2020/185G11B2220/2516G11B2220/415
    • The present inventions are related to systems and methods for pre-equalizer noise suppression in a data processing system. As an example, a data processing system is discussed that includes: a sample averaging circuit, a selector circuit, an equalizer circuit, and a mark detector circuit. The sample averaging circuit is operable to average corresponding data samples from at least a first read of a codeword and a second read of the codeword to yield an averaged output based at least in part on a framing signal. The selector circuit is operable to select one of the averaged output and the first read of the codeword as a selected output. The equalizer circuit is operable to equalize the selected output to yield an equalized output, and the mark detector circuit is operable to identify a location mark in the equalized output to yield the framing signal.
    • 本发明涉及用于数据处理系统中预均衡器噪声抑制的系统和方法。 作为示例,讨论了包括:采样平均电路,选择器电路,均衡器电路和标记检测器电路的数据处理系统。 采样平均电路可用于从码字的至少第一读取和码字的第二读取来平均对应的数据样本,以产生至少部分地基于成帧信号的平均输出。 选择器电路可操作以选择平均输出和码字的第一读取中的一个作为选择的输出。 均衡器电路可操作以均衡所选择的输出以产生均衡的输出,并且标记检测器电路可操作以识别均衡输出中的位置标记以产生成帧信号。
    • 5. 发明申请
    • Systems and Methods for Data Processing Including Pre-Equalizer Noise Suppression
    • 用于数据处理的系统和方法,包括均衡器噪声抑制
    • US20130235920A1
    • 2013-09-12
    • US13415326
    • 2012-03-08
    • Shaohua YangJin Lu
    • Shaohua YangJin Lu
    • H04L27/01
    • G11B20/10046G11B20/10379G11B20/1816G11B2020/1287G11B2020/183G11B2020/185G11B2220/2516G11B2220/415
    • The present inventions are related to systems and methods for pre-equalizer noise suppression in a data processing system. As an example, a data processing system is discussed that includes: a sample averaging circuit, a selector circuit, an equalizer circuit, and a mark detector circuit. The sample averaging circuit is operable to average corresponding data samples from at least a first read of a codeword and a second read of the codeword to yield an averaged output based at least in part on a framing signal. The selector circuit is operable to select one of the averaged output and the first read of the codeword as a selected output. The equalizer circuit is operable to equalize the selected output to yield an equalized output, and the mark detector circuit is operable to identify a location mark in the equalized output to yield the framing signal.
    • 本发明涉及用于数据处理系统中预均衡器噪声抑制的系统和方法。 作为示例,讨论了包括:采样平均电路,选择器电路,均衡器电路和标记检测器电路的数据处理系统。 采样平均电路可用于从码字的至少第一读取和码字的第二读取来平均对应的数据样本,以产生至少部分地基于成帧信号的平均输出。 选择器电路可操作以选择平均输出和码字的第一读取中的一个作为选择的输出。 均衡器电路可操作以均衡所选择的输出以产生均衡的输出,并且标记检测器电路可操作以识别均衡输出中的位置标记以产生成帧信号。
    • 6. 发明授权
    • Cycle slip detection and correction
    • 循环滑移检测和校正
    • US08413014B2
    • 2013-04-02
    • US12511664
    • 2009-07-29
    • Jin LuKeith G. Boyer
    • Jin LuKeith G. Boyer
    • G11C29/42G11C29/00
    • H03M13/1102G11B20/18G11B2020/185G11B2220/90H03M13/03H03M13/033H03M13/41H03M13/6331H03M13/6343
    • A method of writing data to and reading data from a storage medium includes cycle slip detection and correction. An LDPC matrix includes a first area for cycle slip detection and correction. The first area satisfies a set of conditions such that a cycle slip at a particular position creates a pattern of parity check errors indicative of the position and polarity of the cycle slip. Writing user data to the storage medium includes encoding the user data with parity data according to the LDPC matrix. Reading the user data and the parity data from the storage medium includes decoding the user data and the parity data according to the LDPC matrix. Decoding includes, upon detecting a pattern of parity check errors indicative of the position and polarity of a detected cycle slip, correcting the detected cycle slip.
    • 将数据写入存储介质并从存储介质读取数据的方法包括循环滑移检测和校正。 LDPC矩阵包括用于循环滑移检测和校正的第一区域。 第一区域满足一组条件,使得特定位置处的循环滑移创建指示循环滑移的位置和极性的奇偶校验错误的模式。 将用户数据写入存储介质包括根据LDPC矩阵对具有奇偶校验数据的用户数据进行编码。 从存储介质读取用户数据和奇偶校验数据包括根据LDPC矩阵对用户数据和奇偶校验数据进行解码。 解码包括在检测到指示检测到的循环滑移的位置和极性的奇偶校验错误的模式时,校正检测到的循环滑移。
    • 9. 发明授权
    • System and method for reverse error correction coding
    • 用于反向纠错编码的系统和方法
    • US07409622B1
    • 2008-08-05
    • US11272265
    • 2005-11-10
    • Jin LuKeith G. Boyer
    • Jin LuKeith G. Boyer
    • H03M13/00
    • H03M13/31H03M5/145H03M13/1102H03M13/15H03M13/1515H03M13/27
    • A system and method for Reverse Error Correction Coding. The system includes a Constraint encoder, an Error Correction Code encoder, and a uniform interleaver. The Constraint encoder receives a source data stream and generates a first intermediate encoded data stream satisfying a first predetermined timing data constraint. The Error Correction Code encoder receives the first intermediate encoded data stream and generates a second intermediate encoded data stream having one or more Error Correction Code based elements. The uniform interleaver receives the second intermediate encoded data stream and generates a channel data stream having the one or more Error Correction Code based elements and satisfying a second predetermined timing data constraint.
    • 一种用于反向纠错编码的系统和方法。 该系统包括约束编码器,纠错码编码器和统一交织器。 约束编码器接收源数据流并产生满足第一预定定时数据约束的第一中间编码数据流。 纠错码编码器接收第一中间编码数据流并产生具有一个或多个基于错误校正码的元件的第二中间编码数据流。 均匀交织器接收第二中间编码数据流,并产生具有一个或多个基于错误纠正码的元素并满足第二预定定时数据约束的信道数据流。