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1. 发明授权

US06793749B2 Automated method of attaching flip-chip devices to a substrate 有权
标题翻译：将倒装芯片器件连接到衬底的自动化方法
公开(公告)号：US06793749B2
公开(公告)日：2004-09-21
申请号：US10357631
申请日：2003-02-03
申请人： Rich Fogal , John VanNortwick , Chad A. Cobbley
发明人： Rich Fogal , John VanNortwick , Chad A. Cobbley
IPC分类号： B32B3100
CPC分类号： H01L21/67259 , H01L21/67144 , H01L21/6838 , H01L24/48 , H01L24/78 , H01L24/85 , H01L2224/32225 , H01L2224/48091 , H01L2224/4824 , H01L2224/73215 , H01L2224/78 , H01L2224/85 , H01L2924/00014 , H01L2924/14 , Y10T156/1089 , Y10T156/109 , Y10T156/1702 , Y10T156/1744 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： Apparatus and method for attaching, assembling, and/or mounting a substrate to any semiconductor device or a flip-chip type semiconductor device.
摘要翻译：用于将衬底附接，组装和/或安装到任何半导体器件或倒装芯片型半导体器件的装置和方法。

2. 发明授权

US06773523B2 Automated method of attaching flip chip devices to a substrate 失效
标题翻译：将倒装芯片器件连接到衬底的自动化方法
公开(公告)号：US06773523B2
公开(公告)日：2004-08-10
申请号：US10035693
申请日：2001-11-07
申请人： Rich Fogal , John VanNortwick , Chad A. Cobbley
发明人： Rich Fogal , John VanNortwick , Chad A. Cobbley
IPC分类号： B32B3100
CPC分类号： H01L21/67259 , H01L21/67144 , H01L21/6838 , H01L24/48 , H01L24/78 , H01L24/85 , H01L2224/32225 , H01L2224/48091 , H01L2224/4824 , H01L2224/73215 , H01L2224/78 , H01L2224/85 , H01L2924/00014 , H01L2924/14 , Y10T156/1089 , Y10T156/109 , Y10T156/1702 , Y10T156/1744 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： Apparatus and method for attaching, assembling, and/or mounting a substrate to any semiconductor device or a flip-chip type semiconductor device.
摘要翻译：用于将衬底附接，组装和/或安装到任何半导体器件或倒装芯片型半导体器件的装置和方法。

3. 发明授权

US06537400B1 Automated method of attaching flip chip devices to a substrate 有权
公开(公告)号：US06537400B1
公开(公告)日：2003-03-25
申请号：US09520377
申请日：2000-03-06
申请人： Rich Fogal , John VanNortwick , Chad A. Cobbley
发明人： Rich Fogal , John VanNortwick , Chad A. Cobbley
IPC分类号： B32B3100
CPC分类号： H01L21/67259 , H01L21/67144 , H01L21/6838 , H01L24/48 , H01L24/78 , H01L24/85 , H01L2224/32225 , H01L2224/48091 , H01L2224/4824 , H01L2224/73215 , H01L2224/78 , H01L2224/85 , H01L2924/00014 , H01L2924/14 , Y10T156/1089 , Y10T156/109 , Y10T156/1702 , Y10T156/1744 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： Apparatus and method for attaching, assembling, and/or mounting a substrate to any semiconductor device or a flip-chip type semiconductor device.

4. 发明授权

US07476277B2 Apparatus for improving stencil/screen print quality 失效
标题翻译：提高模板/丝网印刷质量的设备
公开(公告)号：US07476277B2
公开(公告)日：2009-01-13
申请号：US10701140
申请日：2003-11-04
申请人： Tongbi Jiang , Chad A. Cobbley , John VanNortwick
发明人： Tongbi Jiang , Chad A. Cobbley , John VanNortwick
IPC分类号： B05C11/00
CPC分类号： B41C1/14 , B41N1/242 , H01L2224/4826 , H05K3/1225 , Y10S438/945
摘要： A method and apparatus for improved stencil/screen print quality is disclosed. The stencil or screen assists in application of a printable material onto a substrate, such as an adhesive to a semiconductor die of a semiconductor wafer during a lead-on-chip (LOC) packaging process. In one embodiment, the stencil includes a coating applied to at least one surface of a pattern of the stencil or screen to retard running of the printable material onto the surface. In another embodiment, the stencil or screen includes a second coating applied to at least one other surface of the pattern to promote spreading of the printable material onto the substrate.
摘要翻译：公开了一种用于改进模板/丝网印刷质量的方法和装置。在片上（LOC）包装过程中，模板或屏幕有助于将可印刷材料施加到基底上，例如对半导体晶片的半导体管芯的粘合剂。在一个实施例中，模板包括施加到模板或筛网的图案的至少一个表面上的涂层，以阻止可印刷材料运动到表面上。在另一个实施例中，模板或丝网包括施加到图案的至少一个其他表面的第二涂层，以促进可印刷材料在基底上的铺展。

5. 发明授权

US07105366B2 Method for in-line testing of flip-chip semiconductor assemblies 失效
公开(公告)号：US07105366B2
公开(公告)日：2006-09-12
申请号：US10338522
申请日：2005-09-08
申请人： Chad A. Cobbley , John VanNortwick , Bret K. Street , Tongbi Jiang
发明人： Chad A. Cobbley , John VanNortwick , Bret K. Street , Tongbi Jiang
IPC分类号： G01R31/26
CPC分类号： G01R1/0483 , Y10T29/4913 , Y10T29/49144
摘要： Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.

6. 发明授权

US07005878B2 Method for in-line testing of flip-chip semiconductor assemblies 失效
公开(公告)号：US07005878B2
公开(公告)日：2006-02-28
申请号：US10900610
申请日：2004-07-27
申请人： Chad A. Cobbley , John VanNortwick , Bret K. Street , Tongbi Jiang
发明人： Chad A. Cobbley , John VanNortwick , Bret K. Street , Tongbi Jiang
IPC分类号： G01R31/26
CPC分类号： G01R1/0483 , Y10T29/4913 , Y10T29/49144
摘要： Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.

7. 发明授权

US06369602B1 Method for in-line testing of flip-chip semiconductor assemblies 失效
标题翻译：倒装芯片半导体组件的在线测试方法
公开(公告)号：US06369602B1
公开(公告)日：2002-04-09
申请号：US09645902
申请日：2000-08-25
申请人： Chad A. Cobbley , John VanNortwick , Bret K. Street , Tongbi Jiang
发明人： Chad A. Cobbley , John VanNortwick , Bret K. Street , Tongbi Jiang
IPC分类号： G01R3126
CPC分类号： G01R1/0483 , Y10T29/4913 , Y10T29/49144
摘要： Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die-attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.
摘要翻译：每个包括集成电路（IC）裸片和相关衬底的倒装芯片半导体组件在封装之前使用在线或原位测试插座或芯片附接站的探针进行电测试。在通过将集成电路（IC）芯片压在基板上的互连点进行电连接而使环氧树脂固化之前，可以测试使用“湿”快速固化环氧树脂进行芯片附着的那些组件，而使用“干”环氧树脂可以在测试之前治愈。在任一种情况下，骰子或骰子与基板之间的互连中的任何故障都可以很容易地固定，并且消除了在维修期间使用已知好模具（KGD）返工程序的需要。

8. 发明授权

US07074648B2 Method for packaging flip-chip semiconductor assemblies 失效
标题翻译：封装倒装芯片半导体组件的方法
公开(公告)号：US07074648B2
公开(公告)日：2006-07-11
申请号：US10714188
申请日：2003-11-14
申请人： Chad A. Cobbley , John VanNortwick , Bret K. Street , Tongbi Jiang
发明人： Chad A. Cobbley , John VanNortwick , Bret K. Street , Tongbi Jiang
IPC分类号： H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： G01R1/0483 , Y10T29/4913 , Y10T29/49144
摘要： Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.
摘要翻译：每个包括集成电路（IC）裸片和相关衬底的倒装芯片半导体组件在封装之前使用在线或原位测试插座或芯片附着站的探针进行电测试。在通过将集成电路（IC）芯片压在基板上的互连点以进行电连接的环氧树脂固化之前，可以测试使用“湿”快速固化环氧树脂进行芯片附接的那些组件，而使用“干”环氧树脂的那些组件在测试之前进行治愈。在任一种情况下，骰子或骰子与基板之间的互连中的任何故障都可以很容易地固定，并且消除了在维修期间使用已知好模具（KGD）返工程序的需要。

9. 发明授权

US06953699B2 Method for in-line testing of flip-chip semiconductor assemblies 失效
公开(公告)号：US06953699B2
公开(公告)日：2005-10-11
申请号：US10900602
申请日：2004-07-27
申请人： Chad A. Cobbley , John VanNortwick , Bret K. Street , Tongbi Jiang
发明人： Chad A. Cobbley , John VanNortwick , Bret K. Street , Tongbi Jiang
IPC分类号： G01R1/04 , G01R31/26
CPC分类号： G01R1/0483 , Y10T29/4913 , Y10T29/49144
摘要： Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.

10. 发明授权

US06599365B1 Apparatus for improving stencil/screen print quality 失效
公开(公告)号：US06599365B1
公开(公告)日：2003-07-29
申请号：US09513628
申请日：2000-02-28
申请人： Tongbi Jiang , Chad A. Cobbley , John VanNortwick
发明人： Tongbi Jiang , Chad A. Cobbley , John VanNortwick
IPC分类号： B05C1111
CPC分类号： B41C1/14 , B41N1/242 , H01L2224/4826 , H05K3/1225 , Y10S438/945
摘要： A method and apparatus for improved stencil/screen print quality is disclosed. The stencil or screen assists in application of a printable material onto a substrate, such as an adhesive to a semiconductor die of a semiconductor wafer during a lead-on-chip (LOC) packaging process. In one embodiment, the stencil includes a coating applied to at least one surface of a pattern of the stencil or screen to retard running of the printable material onto the surface. In another embodiment, the stencil or screen includes a second coating applied to at least one other surface of the pattern to promote spreading of the printable material onto the substrate.

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