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1. 发明授权

US09083353B2 Semiconductor device and electronic device 有权
标题翻译：半导体器件和电子器件
公开(公告)号：US09083353B2
公开(公告)日：2015-07-14
申请号：US13952590
申请日：2013-07-27
申请人： Renesas Mobile Corporation
发明人： Hajime Sasaki , Hirohiko Ito , Shikiko Nachi , Takanobu Naruse
IPC分类号： H03K5/01 , H03L7/08 , G06F1/10 , H03K5/135
CPC分类号： H03L7/08 , G06F1/10 , H03K5/135 , H03L7/18
摘要： A semiconductor device includes a clock input circuit that receives an external clock signal, a PLL circuit for input timing control that performs phase adjustment between the external clock signal and a delayed clock signal to generate an internal clock signal used to acquire input data, and a delay circuit that delays the internal clock signal to output the internal clock signal that is delayed to a PLL circuit for input timing control as a delayed clock signal. The semiconductor device further includes a PLL circuit for output timing control that performs phase adjustment between the external clock signal and a delayed clock signal to generate an internal clock signal used to output output data, and a delay circuit that delays the internal clock signal to output the internal clock signal that is delayed to the PLL circuit for output timing control as a delayed clock signal.
摘要翻译：半导体器件包括接收外部时钟信号的时钟输入电路，用于输入定时控制的PLL电路，其执行外部时钟信号和延迟时钟信号之间的相位调整，以产生用于获取输入数据的内部时钟信号;以及延迟电路延迟内部时钟信号以将延迟到PLL电路的内部时钟信号输出作为延迟时钟信号进行输入定时控制。半导体器件还包括用于输出定时控制的PLL电路，其执行外部时钟信号和延迟时钟信号之间的相位调整，以产生用于输出输出数据的内部时钟信号;以及延迟电路，其将内部时钟信号延迟到输出将延迟到PLL电路的内部时钟信号作为延迟时钟信号进行输出定时控制。

2. 发明申请

US20140043075A1 SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE 有权
标题翻译：半导体器件和电子器件
公开(公告)号：US20140043075A1
公开(公告)日：2014-02-13
申请号：US13952590
申请日：2013-07-27
申请人： Renesas Mobile Corporation
发明人： Hajime Sasaki , Hirohiko Ito , Shikiko Nachi , Takanobu Naruse
IPC分类号： H03L7/08
CPC分类号： H03L7/08 , G06F1/10 , H03K5/135 , H03L7/18
摘要： A semiconductor device includes a clock input circuit that receives an external clock signal, a PLL circuit for input timing control that performs phase adjustment between the external clock signal and a delayed clock signal to generate an internal clock signal used to acquire input data, and a delay circuit that delays the internal clock signal to output the internal clock signal that is delayed to a PLL circuit for input timing control as a delayed clock signal. The semiconductor device further includes a PLL circuit for output timing control that performs phase adjustment between the external clock signal and a delayed clock signal to generate an internal clock signal used to output output data, and a delay circuit that delays the internal clock signal to output the internal clock signal that is delayed to the PLL circuit for output timing control as a delayed clock signal.
摘要翻译：半导体器件包括接收外部时钟信号的时钟输入电路，用于输入定时控制的PLL电路，其执行外部时钟信号和延迟时钟信号之间的相位调整，以产生用于获取输入数据的内部时钟信号;以及延迟电路延迟内部时钟信号以将延迟到PLL电路的内部时钟信号输出作为延迟时钟信号进行输入定时控制。半导体器件还包括用于输出定时控制的PLL电路，其执行外部时钟信号和延迟时钟信号之间的相位调整，以产生用于输出输出数据的内部时钟信号;以及延迟电路，其将内部时钟信号延迟到输出将延迟到PLL电路的内部时钟信号作为延迟时钟信号进行输出定时控制。

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