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1. 发明申请

US20140189259A1 SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE 有权
标题翻译：半导体器件和电子器件
公开(公告)号：US20140189259A1
公开(公告)日：2014-07-03
申请号：US14083608
申请日：2013-11-19
申请人： Renesas Mobile Corporation
发明人： Kenichiro Omura , Ryohei Yoshida , Takanobu Naruse , Seiichi Saito
IPC分类号： G06F13/16 , G06F12/08
CPC分类号： G06F13/1663 , G06F12/0813
摘要： A semiconductor device includes a first memory controller configured to output a first control signal to first and second external memories through a first memory interface, a second memory controller configured to output a second control signal to the second external memory through a second memory interface, an inter-device interface for communicating with another semiconductor device, terminals configured to output the second control signal that has passed through the second memory interface, and a first selector configured to select between the second memory interface and the inter-device interface in accordance with an operation mode of the semiconductor device and to couple the selected interface to the terminals.
摘要翻译：半导体器件包括：第一存储器控制器，被配置为通过第一存储器接口将第一控制信号输出到第一和第二外部存储器;第二存储器控制器，被配置为通过第二存储器接口将第二控制信号输出到第二外部存储器; 用于与另一半导体器件进行通信的设备间接口，被配置为输出已经通过第二存储器接口的第二控制信号的终端;以及第一选择器，被配置为在第二存储器接口和设备间接口之间根据操作模式并将所选择的接口耦合到终端。

2. 发明申请

US20130311849A1 SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE, ELECTRONIC SYSTEM, AND METHOD OF CONTROLLING ELECTRONIC DEVICE 审中-公开
标题翻译：半导体器件，电子器件，电子系统和控制电子器件的方法
公开(公告)号：US20130311849A1
公开(公告)日：2013-11-21
申请号：US13898548
申请日：2013-05-21
申请人： Renesas Mobile Corporation
发明人： Kosuke Miyachi , Kenichiro Omura , Daisuke Kawakami , Hiroshi Morita
IPC分类号： H03M13/29
CPC分类号： H03M13/29 , G06F11/10 , G06F11/1004 , G06F11/1008 , G06F11/1012 , G06F11/1048 , G06F11/1068 , G06F11/1072 , G06F12/0804 , G11C11/5635 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/3436 , G11C16/344
摘要： A storage device holds data and error correcting codes. An LUT stores a relation between a memory address and an error correction level. An error detection level processing unit calculates, based on an access address included in an access instruction to the storage device and the LUT, the error correction level corresponding to the access address. The write controller calculates an error correcting code based on the error correction level that is calculated, and writes the error correcting code together with data in the storage device. A read controller performs error correction processing using the error correcting code based on the error correction level that is calculated, to supply data after error correction.
摘要翻译：存储设备保存数据和纠错码。 LUT存储存储器地址和纠错级别之间的关系。错误检测级别处理单元基于存储设备和LUT的访问指令中包括的访问地址来计算与访问地址对应的错误校正级别。写控制器基于所计算的纠错等级计算纠错码，并将纠错码与数据一起写入存储装置。读取控制器基于所计算的误差校正电平，使用纠错码执行纠错处理，以在纠错后提供数据。

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