专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09251886B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US09251886B2
公开(公告)日：2016-02-02
申请号：US14807957
申请日：2015-07-24
申请人： Renesas Electronics Corporation
发明人： Tetsuo Fukushi , Atsunori Hirobe , Toshikatsu Jinbo , Muneaki Matsushige
IPC分类号： G11C5/02 , G11C11/4091 , G11C7/14 , G11C11/4097
CPC分类号： G11C5/025 , G11C5/02 , G11C5/14 , G11C7/06 , G11C7/14 , G11C11/4091 , G11C11/4097
摘要： A semiconductor storage device 1 according to an aspect includes a first memory area 11—1 and a second memory area 11—2. Memory cells MC_m_n and bit lines BL1, BL2_, . . . , BLm— are disposed in a boundary area 18 between the first and second memory areas 11—1 and 11—2. The memory cells MC_m_n disposed in the boundary area 18 includes memory cells into which no data is written, and a line 56 is formed in a place that overlaps memory cells disposed in the boundary area 18 when the boundary area 18 is viewed from the top. As a result, it is possible to increase the integration density of a memory cell array and provide a line in the memory cell array.
摘要翻译：根据本发明的半导体存储装置1包括第一存储区域11-1和第二存储区域11-2。存储单元MC_m_n和位线BL1，BL2_，。。。 BLm-设置在第一和第二存储区域11-1和11-2之间的边界区域18中。设置在边界区域18中的存储单元MC_m_n包括其中没有写入数据的存储单元，并且当从顶部观看边界区域18时，在与边界区域18中重叠的存储单元重叠的位置处形成行56。结果，可以增加存储单元阵列的集成密度并在存储单元阵列中提供一行。

2. 发明授权

US09123391B2 Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：US09123391B2
公开(公告)日：2015-09-01
申请号：US14082320
申请日：2013-11-18
申请人： Renesas Electronics Corporation
发明人： Tetsuo Fukushi , Atsunori Hirobe , Toshikatsu Jinbo , Muneaki Matsushige
IPC分类号： G11C5/02 , G11C11/4097 , G11C7/14
CPC分类号： G11C5/025 , G11C5/02 , G11C5/14 , G11C7/06 , G11C7/14 , G11C11/4091 , G11C11/4097
摘要： A semiconductor storage device 1 according to an aspect includes a first memory area 11—1 and a second memory area 11—2. Memory cells MC_m_n and bit lines BL1, BL2_, . . . . , BLm_are disposed in a boundary area 18 between the first and second memory areas 11—1 and 11—2. The memory cells MC_m_n disposed in the boundary area 18 includes memory cells into which no data is written, and a line 56 is formed in a place that overlaps memory cells disposed in the boundary area 18 when the boundary area 18 is viewed from the top. As a result, it is possible to increase the integration density of a memory cell array and provide a line in the memory cell array.
摘要翻译：根据本发明的半导体存储装置1包括第一存储区域11-1和第二存储区域11-2。存储单元MC_m_n和位线BL1，BL2_，。。。。 BLm_被布置在第一和第二存储区域11-1和11-2之间的边界区域18中。设置在边界区域18中的存储单元MC_m_n包括其中没有写入数据的存储单元，并且当从顶部观看边界区域18时，在与边界区域18中重叠的存储单元重叠的位置处形成行56。结果，可以增加存储单元阵列的集成密度并在存储单元阵列中提供一行。

3. 发明授权

US08699292B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08699292B2
公开(公告)日：2014-04-15
申请号：US13915929
申请日：2013-06-12
申请人： Renesas Electronics Corporation
发明人： Toshikatsu Jinbo
IPC分类号： G11C5/14
CPC分类号： G05F3/16 , G11C5/147
摘要： A semiconductor device in accordance with an aspect of the present invention includes first and second power-supply circuits each of which generates an internal power-supply voltage by converting a voltage value of a power-supply voltage into a different voltage value, a first internal circuit that receives a supply of the internal power-supply voltage from the first power-supply circuit through a first line, a second internal circuit that receives a supply of the internal power-supply voltage from the second power-supply circuit through a second line, an inter-block line that connects the first and second lines to each other, and a control circuit that operates the first and second internal circuits in a predetermined operating cycle, and controls a length of a period during which the first and second internal circuits operate simultaneously.
摘要翻译：根据本发明的一个方面的半导体器件包括第一和第二电源电路，每个电源电路通过将电源电压的电压值转换成不同的电压值来产生内部电源电压，第一内部通过第一线路从第一电源电路接收内部电源电压的电路;第二内部电路，其通过第二线路接收来自第二电源电路的内部电源电压的供应，将第一和第二线路彼此连接的块间线路，以及控制电路，其以预定的工作周期操作第一和第二内部电路，并且控制第一和第二内部电路的时间长度同时操作。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式