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1. 发明申请

US20230077367A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
公开(公告)号：US20230077367A1
公开(公告)日：2023-03-16
申请号：US18057330
申请日：2022-11-21
申请人： RENESAS ELECTRONICS CORPORATION
发明人： Yasuhiro OKAMOTO , Nobuo MACHIDA , Koichi ARAI , Kenichi HISADA , Yasunori YAMASHITA , Satoshi EGUCHI , Hironobu MIYAMOTO , Atsushi SAKAI , Katsumi EIKYU
IPC分类号： H01L29/78 , H01L29/423 , H01L29/36 , H01L29/66 , H01L21/02 , H01L21/04 , H01L29/10 , H01L29/08 , H01L29/16
摘要： A drift layer is formed over a semiconductor substrate which is an SiC substrate. The drift layer includes first to third n-type semiconductor layers and a p-type impurity region. Herein, an impurity concentration of the second n-type semiconductor layer is higher than an impurity concentration of the first n-type semiconductor layer and an impurity concentration of the third n-type semiconductor layer. Also, in plan view, the second semiconductor layer located between the p-type impurity regions adjacent to each other overlaps with at least a part of a gate electrode formed in a trench.

2. 发明申请

US20210028306A1 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE 有权
公开(公告)号：US20210028306A1
公开(公告)日：2021-01-28
申请号：US17060486
申请日：2020-10-01
申请人： RENESAS ELECTRONICS CORPORATION
发明人： Kenichi HISADA , Koichi ARAI , Hironobu MIYAMOTO
IPC分类号： H01L29/78 , H01L29/423 , H01L29/16 , H01L29/66 , H01L21/308 , H01L29/08 , H01L21/04 , H01L21/02 , H01L21/266
摘要： First and second p-type semiconductor regions (electric-field relaxation layers) are formed by ion implantation using a dummy gate and side wall films on both sides of the dummy gate as a mask. In this manner, it is possible to reduce a distance between the first p-type semiconductor region and a trench and a distance between the second p-type semiconductor region and the trench, and symmetry of the first and second p-type semiconductor regions with respect to the trench can be enhanced. As a result, semiconductor elements can be miniaturized, and on-resistance and an electric-field relaxation effect, which are in a trade-off relationship, can be balanced, so that characteristics of the semiconductor elements can be improved.

3. 发明申请

US20190027597A1 SEMICONDUCTOR DEVICE FOR POWER TRANSISTOR 审中-公开
公开(公告)号：US20190027597A1
公开(公告)日：2019-01-24
申请号：US16137279
申请日：2018-09-20
申请人： RENESAS ELECTRONICS CORPORATION
发明人： Yasunori YAMASHITA , Koichi ARAI , Kenichi HISADA
IPC分类号： H01L29/78 , H01L29/66 , H01L21/02 , H01L21/311 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/16 , H01L29/423 , H01L29/45 , H01L29/51
摘要： In a semiconductor device, in a gate insulating film which is formed on/over an inner wall of a trench, the film thickness of a part of a gate insulating film formed so as to cover a corner of the trench is made thicker than the film thickness of apart of the gate insulating film part formed on/over a side face of the trench.

4. 发明申请

US20160035904A1 VERTICAL-CHANNEL TYPE JUNCTION SIC POWER FET AND METHOD OF MANUFACTURING SAME 有权
标题翻译：垂直通道型连接SIC功率FET及其制造方法
公开(公告)号：US20160035904A1
公开(公告)日：2016-02-04
申请号：US14870922
申请日：2015-09-30
申请人： RENESAS ELECTRONICS CORPORATION
发明人： Kenichi HISADA , Koichi ARAI
IPC分类号： H01L29/808 , H01L27/098 , H01L29/06 , H01L29/16 , H01L29/10
CPC分类号： H01L29/8083 , H01L27/098 , H01L29/0692 , H01L29/1066 , H01L29/1095 , H01L29/1608 , H01L29/66037
摘要： In order to secure the performance of a SiC-based JFET having an impurity diffusion rate lower than silicon-based one, a gate depth is secured while precisely controlling a distance between gate regions, instead of forming gate regions by ion implantation into the side wall of a trench. This means that a channel region defined by a gate distance and a gate depth should have a high aspect ratio. Further, due to limitations of process, a gate region is formed within a source region. Formation of a highly doped PN junction between source and gate regions causes various problems such as inevitable increase in junction current. In addition, a markedly high energy ion implantation becomes necessary for the formation of a termination structure. In the invention, provided is a vertical channel type SiC power JFET having a floating gate region below and separated from a source region and between gate regions.
摘要翻译：为了确保杂质扩散率低于硅基的SiC基JFET的性能，确保栅极深度，同时精确地控制栅极区域之间的距离，而不是通过离子注入形成栅极区域到侧壁的沟渠这意味着由栅极距离和栅极深度限定的沟道区域应具有高的纵横比。此外，由于处理的限制，在源极区域内形成栅极区域。在源极和栅极区域之间形成高度掺杂的PN结导致各种问题，例如结电流的不可避免的增加。此外，为了形成端接结构，需要显着高能量的离子注入。在本发明中，提供了一种垂直沟道型SiC功率JFET，其具有位于源极区域之下和栅极区域之下并与源极区分离的浮动栅极区域。

5. 发明申请

US20200161445A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
公开(公告)号：US20200161445A1
公开(公告)日：2020-05-21
申请号：US16597600
申请日：2019-10-09
申请人： RENESAS ELECTRONICS CORPORATION
发明人： Hironobu MIYAMOTO , Yasuhiro OKAMOTO , Kenichi HISADA , Koichi ARAI , Nobuo MACHIDA
IPC分类号： H01L29/66 , H01L29/16 , H01L29/36 , H01L29/417
摘要： An n-type epitaxial layer is formed on an n-type semiconductor substrate made of silicon carbide. p-type body regions are formed in the epitaxial layer, and n-type source region is formed in the body region. On the body region between the source region and the epitaxial layer, a gate electrode is formed via a gate dielectric film, and an interlayer insulating film having an opening is formed so as to cover the gate electrode. A source electrode electrically connected to the source region and the body regions is formed in the opening. A recombination layer is formed between the body region and a basal plane dislocation is a layer having point defect density higher than that of the epitaxial layer located directly under the recombination layer or having a metal added to the epitaxial layer.

6. 发明申请

US20190237577A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
公开(公告)号：US20190237577A1
公开(公告)日：2019-08-01
申请号：US16223839
申请日：2018-12-18
申请人： RENESAS ELECTRONICS CORPORATION
发明人： Yasuhiro OKAMOTO , Nobuo MACHIDA , Koichi ARAI , Kenichi HISADA , Yasunori YAMASHITA , Satoshi EGUCHI , Hironobu MIYAMOTO , Atsushi SAKAI , Katsumi EIKYU
IPC分类号： H01L29/78 , H01L29/16 , H01L29/423 , H01L29/36 , H01L29/66 , H01L21/02 , H01L21/04 , H01L29/10 , H01L29/08
CPC分类号： H01L29/7813 , H01L21/02164 , H01L21/02271 , H01L21/02378 , H01L21/02529 , H01L21/02634 , H01L21/0274 , H01L21/0465 , H01L21/0475 , H01L21/049 , H01L29/0696 , H01L29/0865 , H01L29/0882 , H01L29/1095 , H01L29/1608 , H01L29/36 , H01L29/4236 , H01L29/45 , H01L29/4916 , H01L29/66068
摘要： A drift layer is formed over a semiconductor substrate which is an SiC substrate. The drift layer includes first to third n-type semiconductor layers and a p-type impurity region. Herein, an impurity concentration of the second n-type semiconductor layer is higher than an impurity concentration of the first n-type semiconductor layer and an impurity concentration of the third n-type semiconductor layer. Also, in plan view, the second semiconductor layer located between the p-type impurity regions adjacent to each other overlaps with at least a part of a gate electrode formed in a trench.

7. 发明申请

US20190198663A1 SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20190198663A1
公开(公告)日：2019-06-27
申请号：US16192480
申请日：2018-11-15
申请人： RENESAS ELECTRONICS CORPORATION
发明人： Atsushi SAKAI , Katsumi EIKYU , Satoshi EGUCHI , Nobuo MACHIDA , Koichi ARAI , Yasuhiro OKAMOTO , Kenichi HISADA , Yasunori YAMASHITA
IPC分类号： H01L29/78 , H01L29/16 , H01L29/08 , H01L29/423 , H01L29/66
CPC分类号： H01L29/7813 , H01L29/0865 , H01L29/1608 , H01L29/4236 , H01L29/66068 , H01L29/66734
摘要： To improve characteristics of a semiconductor device. A first p-type semiconductor region having an impurity of a conductivity type opposite from that of a drift layer is arranged in the drift layer below a trench, and a second p-type semiconductor region is further arranged that is spaced at a distance from a region where the trench is formed as seen from above and that has the impurity of the conductivity type opposite from that of the drift layer. The second p-type semiconductor region is configured by a plurality of regions arranged at a space in a Y direction (depth direction in the drawings). Thus, it is possible to reduce the specific on-resistance while maintaining the breakdown voltage of the gate insulating film by providing the first and second p-type semiconductor regions and further by arranging the second p-type semiconductor region spaced by the space.

8. 发明申请

US20170373183A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
公开(公告)号：US20170373183A1
公开(公告)日：2017-12-28
申请号：US15627333
申请日：2017-06-19
申请人： RENESAS ELECTRONICS CORPORATION
发明人： Yasunori YAMASHITA , Koichi ARAI , Kenichi HISADA
IPC分类号： H01L29/78 , H01L21/02 , H01L29/51 , H01L29/45 , H01L21/311 , H01L29/16 , H01L29/10 , H01L29/08 , H01L29/06 , H01L29/66 , H01L29/423
CPC分类号： H01L29/7813 , H01L21/02164 , H01L21/02236 , H01L21/02255 , H01L21/02271 , H01L21/02529 , H01L21/31111 , H01L29/0696 , H01L29/0865 , H01L29/1033 , H01L29/1095 , H01L29/1608 , H01L29/4236 , H01L29/42368 , H01L29/45 , H01L29/513 , H01L29/66068 , H01L29/66734
摘要： In a semiconductor device, in a gate insulating film which is formed on/over an inner wall of a trench, the film thickness of a part of a gate insulating film formed so as to cover a corner of the trench is made thicker than the film thickness of a part of the gate insulating film part formed on/over a side face of the trench.

9. 发明申请

US20210074816A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
公开(公告)号：US20210074816A1
公开(公告)日：2021-03-11
申请号：US16996351
申请日：2020-08-18
申请人： RENESAS ELECTRONICS CORPORATION
发明人： Atsushi SAKAI , Katsumi EIKYU , Yasuhiro OKAMOTO , Kenichi HISADA , Nobuo MACHIDA
IPC分类号： H01L29/16 , H01L29/78 , H01L29/66
摘要： Semiconductor device has a cell region and a peripheral region, and has a drift layer, a trench, an gate dielectric film on an inner wall of the trench, a gate electrode, and a p-type first semiconductor region below the trench in the cell region on a semiconductor substrate. Further, in the peripheral region on the semiconductor substrate, p-type second semiconductor region is formed in the same layer as the p-type first semiconductor region. a width of the p-type first semiconductor region and a width of the p-type second semiconductor region are different.

10. 发明申请

US20180166554A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD 审中-公开
公开(公告)号：US20180166554A1
公开(公告)日：2018-06-14
申请号：US15790195
申请日：2017-10-23
申请人： Renesas Electronics Corporation
发明人： Kenichi HISADA , Koichi ARAI
IPC分类号： H01L29/66 , H01L29/06 , H01L29/16 , H01L23/31 , H01L29/78 , H01L23/29 , H01L21/04 , H01L21/02
CPC分类号： H01L29/66068 , H01L21/02236 , H01L21/02255 , H01L21/02271 , H01L21/045 , H01L21/049 , H01L23/291 , H01L23/3171 , H01L29/0615 , H01L29/0619 , H01L29/063 , H01L29/0634 , H01L29/0692 , H01L29/0696 , H01L29/1608 , H01L29/511 , H01L29/518 , H01L29/7395 , H01L29/7811
摘要： A semiconductor device includes: a first conductivity type semiconductor substrate made of silicon carbide; a second conductivity type body region in a device region of the semiconductor substrate; a first conductivity type source region formed in the body region; and a gate electrode formed on the body region through gate insulating films. The semiconductor device further includes, in a termination region of the semiconductor substrate, second conductivity type RESURF layers, and an edge termination region formed in the RESURF layers. Then, the RESURF layers and a front surface of the semiconductor substrate adjacent to the RESURF layers are covered by an oxidation-resistant insulating film.

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