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1. 发明授权

US10374625B2 Capacitor layout of digital-to-analog conversion integrated circuit 有权
公开(公告)号：US10374625B2
公开(公告)日：2019-08-06
申请号：US15855149
申请日：2017-12-27
申请人： REALTEK SEMICONDUCTOR CORPORATION
发明人： Shih-Hsiung Huang , Sheng-Hsiung Lin
IPC分类号： H03M1/66 , H03M1/80 , H03M1/68 , H03M1/46
摘要： The present invention discloses a capacitor layout of a digital-to-analog conversion integrated circuit (DAC IC), comprising a first capacitor group, a second capacitor group and a third capacitor group. The first capacitor group, located within an interior layout area of the capacitor layout, determines a most significant bit (MSB) of the DAC IC and includes a plurality of capacitor units coupled between a first upper circuit and a first lower circuit. The second capacitor group, located within the interior layout area, determines a non-MSB bit of the DAC IC and includes at least one capacitor unit(s) coupled between a second upper circuit and a second lower circuit. The third capacitor group includes a plurality of capacitor units coupled between a third upper circuit and a third lower circuit which are not short-circuited; the capacitor units of the third capacitor group are disposed around the interior layout area.

2. 发明授权

US09136863B2 Successive approximation analog-to-digital converter and conversion method 有权
标题翻译：逐次逼近模数转换器和转换方法
公开(公告)号：US09136863B2
公开(公告)日：2015-09-15
申请号：US14585812
申请日：2014-12-30
申请人： REALTEK SEMICONDUCTOR CORPORATION
发明人： Sheng-Hsiung Lin
IPC分类号： H03M1/12 , H03M1/38
CPC分类号： H03M1/129 , H03M1/468
摘要： The present invention discloses a successive approximation analog-to-digital converter, comprising: a capacitor array including a designated capacitor and several sampling capacitors to sample an input signal under a sampling mode; a comparator to compare a first voltage from the capacitor array with a second voltage under a comparison mode and thereby generate a comparison result; a switching circuit to determine the charge amount stored in the capacitor array under the sampling mode and the first voltage under the comparison mode according to a control signal; and a control circuit to generate the control signal according to a sampling setting under the sampling mode and generate the control signal according to the comparison result under the comparison mode. Said designated capacitor does no sampling under the sampling mode, but appropriates the charges of the sampling capacitors under the comparison mode, so as to reduce the effective sampling value.
摘要翻译：本发明公开了一种逐次逼近模数转换器，包括：包括指定电容器和几个采样电容器的电容器阵列，以在采样模式下采样输入信号; 比较器，用于在比较模式下将来自电容器阵列的第一电压与第二电压进行比较，从而产生比较结果; 开关电路，用于根据控制信号确定在采样模式下存储在电容器阵列中的电荷量和在比较模式下的第一电压; 以及控制电路，根据采样模式下的采样设定生成控制信号，并根据比较模式下的比较结果生成控制信号。所述指定电容器在采样模式下不进行采样，而是在比较模式下占用采样电容器的电荷，从而降低有效采样值。

3. 发明授权

US11799490B2 Signal converter device, dynamic element matching circuit, and dynamic element matching method 有权
公开(公告)号：US11799490B2
公开(公告)日：2023-10-24
申请号：US17720754
申请日：2022-04-14
申请人： REALTEK SEMICONDUCTOR CORPORATION
发明人： Sheng-Hsiung Lin
IPC分类号： H03M1/06 , H03M7/16 , H03M1/68
CPC分类号： H03M1/066 , H03M1/682 , H03M7/165
摘要： A dynamic element method includes the following operations: summing up most significant bits of a digital code in a previous period and a pointer signal in the previous period, in order to generate a first signal; outputting the first signal to be an adjusted pointer signal according to a clock signal; and decoding the adjusted pointer signal to be control signals, in which the control signals are configured to set corresponding relations of components of a first digital to analog converter circuits and the most significant bits, in order to utilize the components to convert the most significant bits.

4. 发明授权

US10432181B2 Data converter and impedance matching control method thereof 有权
公开(公告)号：US10432181B2
公开(公告)日：2019-10-01
申请号：US15982614
申请日：2018-05-17
申请人： REALTEK SEMICONDUCTOR CORPORATION
发明人： Chih-Lung Chen , Sheng-Hsiung Lin , Jie-Fan Lai , Shih-Hsiung Huang
IPC分类号： H03K5/1252 , H03H11/28 , H03K5/24 , H03M1/12
摘要： A data converter and an impedance matching control method are provided. The data converter includes a comparator, a capacitor array as well as a switch and impedance matching circuit. The comparator includes a first input terminal and a second input terminal. The capacitor array includes a plurality of capacitors, and a first end of each capacitor is coupled to the first input terminal or the second input terminal. The switch and impedance matching circuit is coupled to a second end of a target capacitor among the capacitors and configured to couple the second end to a first reference voltage or a second reference voltage according to a control signal and adjust an impedance according to an impedance adjusting signal, in which the impedance is the impedance of the switch and impedance matching circuit. The first reference voltage is different from the second reference voltage.

5. 发明授权

US10171097B1 Correcting device of successive approximation analog-to-digital conversion 有权
公开(公告)号：US10171097B1
公开(公告)日：2019-01-01
申请号：US16048479
申请日：2018-07-30
申请人： REALTEK SEMICONDUCTOR CORPORATION
发明人： Sheng-Hsiung Lin , Jie-Fan Lai , Liang-Wei Huang , Chih-Lung Chen , Shih-Hsiung Huang
IPC分类号： H03M1/06 , H03M1/08
摘要： Disclosed is a correcting device of successive approximation analog-to-digital conversion. The correcting device includes a successive approximation register analog-to-digital converter (SAR ADC) and a digital circuit. The SAR ADC is configured to generate a digital output. The digital circuit is configured to determine whether the digital output conforms to a metastable output, and correct the digital output when the digital output conforms to the metastable output. The metastable output is related with a metastable binary comparison-results sequence including successive K comparison results such as 110000 or 001111. The K comparison results include a first comparison result, a second comparison result and successive M comparison results in turn. The first comparison result and the second comparison result are the same; the M comparison results are the same; each of the first comparison result and the second comparison result is different from any of the M comparison results.

6. 发明授权

US10862497B1 Successive approximation analog-to-digital converter and operation method thereof 有权
公开(公告)号：US10862497B1
公开(公告)日：2020-12-08
申请号：US16815593
申请日：2020-03-11
申请人： REALTEK SEMICONDUCTOR CORPORATION
发明人： Sheng-Hsiung Lin
IPC分类号： H03M1/12 , H03M1/46
摘要： A successive approximation analog-to-digital converter (SAR ADC) and an operation method thereof are provided. The SAR ADC, which alternately operates in a sampling phase and a comparison and switching phase, includes a switch-capacitor digital-to-analog converter (DAC), a comparator, a successive approximation register and a control circuit. The switch-capacitor DAC including multiple capacitors. The control circuit is configured to (A) control a top plate of a first capacitor and a top plate of a second capacitor to be coupled to an analog input signal during the sampling phase; (B) control the first capacitor and the second capacitor to be active and inactive, respectively, in the comparison and switching phase according to a reference code after the sampling phase finishes; and (C) switch a terminal voltage of at least one of the capacitors during the comparison and switching phase according to the comparison results of the comparator.

7. 发明申请

US20190068179A1 Data converter and impedance matching control method thereof 审中-公开
公开(公告)号：US20190068179A1
公开(公告)日：2019-02-28
申请号：US15982614
申请日：2018-05-17
申请人： Realtek Semiconductor Corporation
发明人： CHIH-LUNG CHEN , Sheng-Hsiung Lin , Jie-Fan Lai , Shih-Hsiung Huang
IPC分类号： H03K5/1252 , H03K5/24 , H03H11/28
CPC分类号： H03K5/1252 , H03H11/28 , H03K5/24 , H03M1/12
摘要： A data converter and an impedance matching control method are provided. The data converter includes a comparator, a capacitor array as well as a switch and impedance matching circuit. The comparator includes a first input terminal and a second input terminal. The capacitor array includes a plurality of capacitors, and a first end of each capacitor is coupled to the first input terminal or the second input terminal. The switch and impedance matching circuit is coupled to a second end of a target capacitor among the capacitors and configured to couple the second end to a first reference voltage or a second reference voltage according to a control signal and adjust an impedance according to an impedance adjusting signal, in which the impedance is the impedance of the switch and impedance matching circuit. The first reference voltage is different from the second reference voltage.

8. 发明申请

US20180337688A1 Capacitor layout of digital-to-analog conversion integrated circuit 审中-公开
公开(公告)号：US20180337688A1
公开(公告)日：2018-11-22
申请号：US15855149
申请日：2017-12-27
申请人： REALTEK SEMICONDUCTOR CORPORATION
发明人： Shih-Hsiung Huang , Sheng-Hsiung Lin
IPC分类号： H03M1/80 , H03M1/68
CPC分类号： H03M1/802 , H03M1/468 , H03M1/68
摘要： The present invention discloses a capacitor layout of a digital-to-analog conversion integrated circuit (DAC IC), comprising a first capacitor group, a second capacitor group and a third capacitor group. The first capacitor group, located within an interior layout area of the capacitor layout, determines a most significant bit (MSB) of the DAC IC and includes a plurality of capacitor units coupled between a first upper circuit and a first lower circuit. The second capacitor group, located within the interior layout area, determines a non-MSB bit of the DAC IC and includes at least one capacitor unit(s) coupled between a second upper circuit and a second lower circuit. The third capacitor group includes a plurality of capacitor units coupled between a third upper circuit and a third lower circuit which are not short-circuited; the capacitor units of the third capacitor group are disposed around the interior layout area.

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