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1. 发明申请

US20130328630A1 POWER AMPLIFIER 有权
标题翻译：功率放大器
公开(公告)号：US20130328630A1
公开(公告)日：2013-12-12
申请号：US13967406
申请日：2013-08-15
申请人： REALTEK SEMICONDUCTOR CORP.
发明人： Po-Chih Wang
IPC分类号： H03F3/45 , H03F3/24
CPC分类号： H03F3/45179 , H03F1/0272 , H03F1/223 , H03F1/3211 , H03F3/193 , H03F3/245 , H03F2200/102 , H03F2200/18 , H03F2200/411 , H03F2200/534 , H03F2200/537 , H03F2200/541 , H03F2200/99 , H03F2203/45112 , H03F2203/45481 , H03F2203/45544 , H03F2203/45554 , H03F2203/45604
摘要： A power amplifier is provided. The power amplifier includes a loading circuit, a first stage amplifying circuit, an analog pre-distorter, a loading circuit and a second stage amplifying circuit. The first stage amplifying circuit is coupled to the loading circuit to receive a first signal and output a second signal accordingly. The analog pre-distorter is coupled to the first stage amplifying circuit to detect the envelope of the second signal and generates a third signal according to the envelope. The second stage amplifying circuit is coupled to the first stage amplifying circuit to receive the second signal. The loading circuit is biased on the third signal. The gain of the first stage amplifying circuit is related to the third signal.
摘要翻译：提供功率放大器。功率放大器包括负载电路，第一级放大电路，模拟预失真器，负载电路和第二级放大电路。第一级放大电路耦合到负载电路以接收第一信号并相应地输出第二信号。模拟预失真器耦合到第一级放大电路以检测第二信号的包络，并根据包络产生第三信号。第二级放大电路耦合到第一级放大电路以接收第二信号。加载电路偏置在第三个信号上。第一级放大电路的增益与第三信号有关。

2. 发明申请

US20230047042A1 Power amplifying circuits 有权
公开(公告)号：US20230047042A1
公开(公告)日：2023-02-16
申请号：US17873176
申请日：2022-07-26
申请人： Realtek Semiconductor Corp.
发明人： Po-Chih Wang , Hsiao-Tsung Yen , Ka-Un Chan
IPC分类号： H03F1/02 , H03F3/21 , H03F1/56
摘要： A power amplifying circuit includes a first input terminal applied with a first bias voltage, a first amplifying circuit generating a first output signal and a second output signal according to an input signal and a first matching circuit combining the first output signal and the second output signal to generate an output signal. The first amplifying circuit includes a first transistor having a first electrode coupled to the first input terminal and a second electrode applied with a second bias voltage and a second transistor having a first electrode s coupled to the first input terminal and a second electrode applied with a third bias voltage. The first transistor generates the first output signal according to the first bias voltage and the second bias voltage. The second transistor generates the second output signal according to the first bias voltage and the third bias voltage.

3. 发明授权

US09214898B2 Triple cascode power amplifier 有权
标题翻译：三重共源共栅功率放大器
公开(公告)号：US09214898B2
公开(公告)日：2015-12-15
申请号：US14158009
申请日：2014-01-17
申请人： Realtek Semiconductor Corp.
发明人： Gen-Sheng Ran , Po-Chih Wang , Ka-Un Chan
IPC分类号： H03F3/04 , H03F1/22 , H03F3/45
CPC分类号： H03F1/223 , H03F3/45179 , H03F2200/09 , H03F2200/18 , H03F2200/372 , H03F2200/555 , H03F2203/45292 , H03F2203/45394 , H03F2203/45701 , H03F2203/45731
摘要： A triple cascode power amplifier is provided. The triple cascode power amplifier includes a first-stage transistor pair, a second-stage transistor pair and a third-stage transistor pair. The first-stage transistor pair comprises two first-stage transistors that respectively receive two dynamic bias voltages with opposite polarities. The second-stage transistor pair is coupled with the first-stage transistor pair to form a first node and comprise two second-stage transistors coupled with each other to form a second node. The third-stage transistor pair is coupled with the second-stage transistor pair and comprises two third-stage transistors for outputting a differential signal. The first-stage transistor pair and the second-stage transistor pair are low voltage components while the third-stage transistor pair is a high voltage component. The power amplifier transforms the differential signal into a single-ended signal for output.
摘要翻译：提供三重共源共栅功率放大器。三级共源共栅功率放大器包括第一级晶体管对，第二级晶体管对和第三级晶体管对。第一级晶体管对包括分别接收具有相反极性的两个动态偏置电压的两个第一级晶体管。第二级晶体管对与第一级晶体管对耦合以形成第一节点并且包括彼此耦合以形成第二节点的两个第二级晶体管。第三级晶体管对与第二级晶体管对耦合，并且包括用于输出差分信号的两个第三级晶体管。第一级晶体管对和第二级晶体管对是低电压分量，而第三级晶体管对是高电压分量。功率放大器将差分信号转换为单端信号进行输出。

4. 发明公开

US20240283405A1 BIAS VOLTAGE GENERATING CIRCUIT 审中-公开
公开(公告)号：US20240283405A1
公开(公告)日：2024-08-22
申请号：US18420711
申请日：2024-01-23
申请人： Realtek Semiconductor Corp.
发明人： Po-Chih Wang
IPC分类号： H03F1/02 , H03F3/21
CPC分类号： H03F1/0205 , H03F3/21
摘要： A bias voltage generating circuit includes a first circuit subunit, a second circuit subunit, and a third circuit subunit. The first circuit subunit is arranged to generate a first bias voltage at a first node in response to a first current and a first input voltage. The second circuit subunit is coupled to the first circuit subunit, and is arranged to receive the first bias voltage and generate a second current flowing through a second node, wherein the second current is mirrored from the first current. The third circuit subunit is coupled to the second node, and is arranged to generate a second bias voltage at a third node in response to the second current and a second input voltage.

5. 发明授权

US11942906B2 Transmitter having harmonic impedance adjustment circuit 有权
公开(公告)号：US11942906B2
公开(公告)日：2024-03-26
申请号：US17666530
申请日：2022-02-07
申请人： Realtek Semiconductor Corp.
发明人： Ting-Yao Huang , Teng-Yuan Chang , Po-Chih Wang , Ka-Un Chan
IPC分类号： H04L27/00 , H03F1/56 , H03F3/19
CPC分类号： H03F1/56 , H03F3/19 , H03F2200/222 , H03F2200/387
摘要： The present invention provides a transmitter including a mixer, a harmonic impedance adjustment circuit and an amplifier. The mixer is configured to mix a first baseband signal with a first oscillation signal to generate a first mixed signal to a first node, and to mix a second baseband signal with a second oscillation signal to generate a second mixed signal to a second node. The harmonic impedance adjustment circuit is coupled between the first node and the second node, and is configured to reduce harmonic components of the first mixed signal and the second mixed signal to generate an adjusted first mixed signal and an adjusted second mixed signal. The amplifier is coupled to the harmonic impedance adjustment circuit, and is configured to generate an amplified signal according to the adjusted first mixed signal and the adjusted second mixed signal.

6. 发明授权

US08665019B2 Power amplifier 有权
标题翻译：功率放大器
公开(公告)号：US08665019B2
公开(公告)日：2014-03-04
申请号：US13967406
申请日：2013-08-15
申请人： Realtek Semiconductor Corp.
发明人： Po-Chih Wang
IPC分类号： H03F3/45
CPC分类号： H03F3/45179 , H03F1/0272 , H03F1/223 , H03F1/3211 , H03F3/193 , H03F3/245 , H03F2200/102 , H03F2200/18 , H03F2200/411 , H03F2200/534 , H03F2200/537 , H03F2200/541 , H03F2200/99 , H03F2203/45112 , H03F2203/45481 , H03F2203/45544 , H03F2203/45554 , H03F2203/45604
摘要： A power amplifier is provided. The power amplifier includes a loading circuit, a first stage amplifying circuit, an analog pre-distorter, a loading circuit and a second stage amplifying circuit. The first stage amplifying circuit is coupled to the loading circuit to receive a first signal and output a second signal accordingly. The analog pre-distorter is coupled to the first stage amplifying circuit to detect the envelope of the second signal and generates a third signal according to the envelope. The second stage amplifying circuit is coupled to the first stage amplifying circuit to receive the second signal. The loading circuit is biased on the third signal. The gain of the first stage amplifying circuit is related to the third signal.
摘要翻译：提供功率放大器。功率放大器包括负载电路，第一级放大电路，模拟预失真器，负载电路和第二级放大电路。第一级放大电路耦合到负载电路以接收第一信号并相应地输出第二信号。模拟预失真器耦合到第一级放大电路以检测第二信号的包络，并根据包络产生第三信号。第二级放大电路耦合到第一级放大电路以接收第二信号。加载电路偏置在第三个信号上。第一级放大电路的增益与第三信号有关。

7. 发明申请

US20220286096A1 TRANSMITTER HAVING HARMONIC IMPEDANCE ADJUSTMENT CIRCUIT 有权
公开(公告)号：US20220286096A1
公开(公告)日：2022-09-08
申请号：US17666530
申请日：2022-02-07
申请人： Realtek Semiconductor Corp.
发明人： Ting-Yao Huang , Teng-Yuan Chang , Po-Chih Wang , Ka-Un Chan
IPC分类号： H03F1/56 , H03F3/19
摘要： The present invention provides a transmitter including a mixer, a harmonic impedance adjustment circuit and an amplifier. The mixer is configured to mix a first baseband signal with a first oscillation signal to generate a first mixed signal to a first node, and to mix a second baseband signal with a second oscillation signal to generate a second mixed signal to a second node. The harmonic impedance adjustment circuit is coupled between the first node and the second node, and is configured to reduce harmonic components of the first mixed signal and the second mixed signal to generate an adjusted first mixed signal and an adjusted second mixed signal. The amplifier is coupled to the harmonic impedance adjustment circuit, and is configured to generate an amplified signal according to the adjusted first mixed signal and the adjusted second mixed signal.

8. 发明授权

US11385668B2 Configurable offset compensation device 有权
公开(公告)号：US11385668B2
公开(公告)日：2022-07-12
申请号：US17234760
申请日：2021-04-19
申请人： Realtek Semiconductor Corp.
发明人： Ting-Yao Huang , Po-Chih Wang , Ka-Un Chan
IPC分类号： G05F3/24
摘要： An offset compensation device includes a first bias module and a second bias module. The first bias module includes a plurality of first current control circuits and a plurality of second current control circuits coupled in parallel. Each of the first current control circuits generates a first reference current, and each of the second current control circuits generates a second reference current. The second bias module includes a plurality of third current control circuits and a plurality of fourth current control circuits coupled in parallel. Each of the third current control circuits generates a third reference current, and each of the fourth current control circuits generates a fourth reference current. The second reference current is greater than the first reference current, and the fourth reference current is greater than the third reference current.

9. 发明授权

US09484150B2 Multi-mode power amplifying circuit, and multi-mode wireless transmission module and method thereof 有权
标题翻译：多模功率放大电路及多模无线传输模块及其方法
公开(公告)号：US09484150B2
公开(公告)日：2016-11-01
申请号：US14045213
申请日：2013-10-03
申请人： REALTEK SEMICONDUCTOR CORP.
发明人： Po-Chih Wang , Ya-Wen Yang
IPC分类号： H01F38/14 , H04B1/04 , H03F1/02 , H03F3/34
CPC分类号： H01F38/14 , H03F1/0277 , H03F3/24 , H03F3/34 , H04B1/0458
摘要： A multi-mode power amplifying circuit, and a multi-mode wireless transmission module and method thereof are provided. The multi-mode wireless transmission module includes the multi-mode power amplifying circuit and an antenna. In the multi-mode power amplifying circuit and the antenna, a first power amplifier is electrically connected between a signal input end and a first impedance matching circuit, and an output end of the first impedance matching circuit is electrically connected to the antenna. A second power amplifier is electrically connected to the signal input end, and a second impedance matching circuit is electrically connected between the second power amplifier and the first impedance matching circuit. A switching circuit is electrically connected to an input end of the second impedance matching circuit. The switching circuit switches on-off corresponding to an operation of the first power amplifier and an operation of the second power amplifier.
摘要翻译：提供了一种多模式功率放大电路以及多模式无线传输模块及其方法。多模无线传输模块包括多模功率放大电路和天线。在多模式功率放大电路和天线中，第一功率放大器电连接在信号输入端和第一阻抗匹配电路之间，第一阻抗匹配电路的输出端电连接到天线。第二功率放大器电连接到信号输入端，并且第二阻抗匹配电路电连接在第二功率放大器和第一阻抗匹配电路之间。开关电路电连接到第二阻抗匹配电路的输入端。开关电路对应于第一功率放大器的操作和第二功率放大器的操作而导通 - 断开。

10. 发明申请

US20210333816A1 CONFIGURABLE OFFSET COMPENSATION DEVICE 有权
公开(公告)号：US20210333816A1
公开(公告)日：2021-10-28
申请号：US17234760
申请日：2021-04-19
申请人： Realtek Semiconductor Corp.
发明人： Ting-Yao Huang , Po-Chih Wang , Ka-Un Chan
IPC分类号： G05F3/24
摘要： An offset compensation device includes a first bias module and a second bias module. The first bias module includes a plurality of first current control circuits and a plurality of second current control circuits coupled in parallel. Each of the first current control circuits generates a first reference current, and each of the second current control circuits generates a second reference current. The second bias module includes a plurality of third current control circuits and a plurality of fourth current control circuits coupled in parallel. Each of the third current control circuits generates a third reference current, and each of the fourth current control circuits generates a fourth reference current. The second reference current is greater than the first reference current, and the fourth reference current is greater than the third reference current.

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