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1. 发明授权

US6047382A Processor with short set-up and hold times for bus signals 有权
标题翻译：具有短路设置和保持时间的处理器，用于总线信号
公开(公告)号：US6047382A
公开(公告)日：2000-04-04
申请号：US168354
申请日：1998-10-07
申请人： Reading G. Maley , Amos Ben-Meir , Anil Mehta
发明人： Reading G. Maley , Amos Ben-Meir , Anil Mehta
IPC分类号： G06F1/12 , G06F13/40 , H04L7/00 , G06F1/06
CPC分类号： G06F1/12 , G06F13/4072 , H04L7/0012
摘要： A processor includes a system bus interface that permits short set-up and hold times for bus signals including loop-back signals. Loop-back signals are transferred from an input cell in the interface to a target I/O cell in the interface without resynchronizing the loop-back signal with the processor clock. Accordingly, set-up and hold times for the loop-back signal need only be sufficient to allow for jitter or uncompensated delay in the bus clock signal at the target I/O cell. The processing core provides valid signals that might be required for generating an output signal from the target cell. The core avoids changing those signals near triggering edges of the bus clock signal to prevent the signals from changing before the target I/O cell uses the required signals. Typically, the loop-back signal determines whether I/O cell is enabled for output and is also used at the edge of the bus clock signal.
摘要翻译：处理器包括系统总线接口，其允许包括环回信号的总线信号的短暂建立和保持时间。环回信号从接口中的输入单元传送到接口中的目标I / O单元，而不会使环回信号与处理器时钟重新同步。因此，环回信号的设置和保持时间仅需足以允许目标I / O单元处的总线时钟信号中的抖动或无补偿的延迟。处理核心提供从目标单元产生输出信号可能需要的有效信号。内核避免在总线时钟信号的触发边缘附近改变这些信号，以防止信号在目标I / O单元使用所需信号之前改变。通常，环回信号确定I / O单元是否被使能以用于输出，并且也用于总线时钟信号的边沿。

2. 发明授权

US5915107A Cross clock domain clocking for a system using two clock frequencies where one frequency is fractional multiple of the other 失效
$Cross clock domain clocking for a system using two clock frequencies where one frequency is fractional multiple of the other$
标题翻译：对于使用两个时钟频率的系统的跨时钟域时钟，其中一个频率是另一个频率的分数倍
公开(公告)号：US5915107A
公开(公告)日：1999-06-22
申请号：US938205
申请日：1997-09-26
申请人： Reading G. Maley , Amos Ben-Meir , Anil Mehta
发明人： Reading G. Maley , Amos Ben-Meir , Anil Mehta
IPC分类号： G06F1/12 , G06F13/40 , H04L7/00 , G06F1/06
CPC分类号： H04L7/0012 , G06F1/12 , G06F13/4072
摘要： A processor includes a processing core that is operable at a frequency that is an odd half-integer multiple of a bus clock frequency. Signals on a system bus are synchronized with a selected edge, e.g., the rising edge, of a bus clock signal, but the processing core requires signals synchronized with a processor clock signal. Signal crossing between the clock domain of the processing core and the clock domain of the system bus pass through a storage element that selectably latches a value of the signal either at a rising edge or a falling edge of the processor clock signal. A control circuit selects either rising-edge or falling-edge latching depending on which edge (rising or falling) is closest to being synchronized with the selected edge of the bus clock signal.
摘要翻译：处理器包括可以以总线时钟频率的奇数半整数倍的频率工作的处理核心。系统总线上的信号与总线时钟信号的选定边沿（例如上升沿）同步，但处理核心需要与处理器时钟信号同步的信号。处理核心的时钟域与系统总线的时钟域之间的信号交叉通过存储元件，该存储元件在处理器时钟信号的上升沿或下降沿可选地锁存该信号的值。控制电路根据哪个边沿（上升沿或下降沿）最接近于与总线时钟信号的选定边沿同步而选择上升沿或下降沿锁存。

3. 发明授权

US06278181B1 Stacked multi-chip modules using C4 interconnect technology having improved thermal management 有权
标题翻译：使用C4互连技术的堆叠多芯片模块具有改进的热管理
公开(公告)号：US06278181B1
公开(公告)日：2001-08-21
申请号：US09340419
申请日：1999-06-28
申请人： Reading G. Maley
发明人： Reading G. Maley
IPC分类号： H01L2352
CPC分类号： H01L25/0657 , H01L23/3677 , H01L23/3737 , H01L23/473 , H01L23/481 , H01L24/48 , H01L24/81 , H01L2224/05124 , H01L2224/05147 , H01L2224/05554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16145 , H01L2224/16225 , H01L2224/48091 , H01L2224/81801 , H01L2225/06513 , H01L2225/06524 , H01L2225/06541 , H01L2225/06589 , H01L2225/06596 , H01L2924/00014 , H01L2924/00015 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01077 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/10162 , H01L2924/13091 , H01L2924/14 , H01L2924/30107 , H01L2924/00 , H01L2224/05599 , H01L2224/45099 , H01L2224/85399 , H01L2224/45015 , H01L2924/207
摘要： A flip-chip circuit arrangement having improved thermal management includes a base substrate having a top surface which includes one or more bond pads thereon. The arrangement further includes a semiconductor substrate having circuitry and one or more bond pads thereon, wherein the one or more bond pads on the semiconductor substrate correspond to the one or more bond pads on the base substrate. The semiconductor substrate has one or more channels which extend from a top surface to a bottom surface thereof and the channels facilitate a transfer of heat due to power dissipation of the circuitry away from the semiconductor substrate.
摘要翻译：具有改进的热管理的倒装芯片电路装置包括具有顶表面的基底基底，其上包括一个或多个接合垫。该布置还包括具有电路和其上的一个或多个接合焊盘的半导体衬底，其中半导体衬底上的一个或多个接合焊盘对应于基底衬底上的一个或多个接合焊盘。半导体衬底具有从顶表面延伸到其底表面的一个或多个通道，并且由于电路的功率消耗远离半导体衬底，通道有助于热传递。

4. 发明授权

US07613756B1 Random number generation apparatus and method 有权
标题翻译：随机数生成装置和方法
公开(公告)号：US07613756B1
公开(公告)日：2009-11-03
申请号：US11034074
申请日：2005-01-11
申请人： Xiaojun Zhu , Reading G. Maley , Sompur M. Shivakumar
发明人： Xiaojun Zhu , Reading G. Maley , Sompur M. Shivakumar
IPC分类号： G06F7/58
CPC分类号： G06F7/588
摘要： An apparatus and a method are provided for generating a random number, wherein the randomness of the random number is derived from thermal noise present across a pair of resistors. Each of the pair of resistors is defined to receive a respective input voltage and add a respective noise component to the input voltage. The output from each resistor in the pair of resistors is amplified to generate a noisy analog voltage that includes a representation of the random noise components added by the pair of resistors. The randomly varying noisy analog voltage is used to control a voltage controlled oscillator (VCO). The VCO generates a random digital signal based on the randomly varying noisy analog voltage. The random digital signal generated by the VCO is used to set a number of bits for defining a random number.
摘要翻译：提供了一种用于产生随机数的装置和方法，其中随机数的随机性源自存在于一对电阻器上的热噪声。一对电阻器中的每一个被限定为接收相应的输入电压并将相应的噪声分量加到输入电压上。一对电阻器中的每个电阻器的输出被放大以产生噪声模拟电压，其包括由该对电阻器添加的随机噪声分量的表示。随机变化的噪声模拟电压用于控制压控振荡器（VCO）。 VCO基于随机变化的噪声模拟电压产生随机数字信号。由VCO生成的随机数字信号用于设定用于定义随机数的位数。

5. 发明授权

US06249136B1 Bottom side C4 bumps for integrated circuits 失效
公开(公告)号：US06249136B1
公开(公告)日：2001-06-19
申请号：US09340418
申请日：1999-06-28
申请人： Reading G. Maley
发明人： Reading G. Maley
IPC分类号： G01R3128
CPC分类号： H01L25/0657 , G01R31/2884 , G01R31/307 , H01L21/76898 , H01L22/32 , H01L23/481 , H01L24/11 , H01L24/48 , H01L25/50 , H01L2224/05554 , H01L2224/05568 , H01L2224/05573 , H01L2224/13099 , H01L2224/16 , H01L2224/48091 , H01L2225/06513 , H01L2225/06541 , H01L2225/06589 , H01L2924/00014 , H01L2924/00015 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01077 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/10162 , H01L2924/13091 , H01L2924/14 , H01L2924/30107 , H01L2924/00 , H01L2224/85399 , H01L2224/05599 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method of forming a test configuration for an integrated circuit employing a controlled, collapse chip connection technology to attach to another substrate is disclosed. The method includes the steps of forming one or more vias in a semiconductor substrate corresponding to the integrated circuit and forming circuitry on a top surface of the semiconductor substrate. The method further includes filling the one or more vias with a conductive material to form conductive channels through the semiconductor substrate which selectively couples to the circuitry to provide control signals thereto and receive output signals therefrom. One or more bond pads are formed on a bottom surface of the semiconductor substrate and correspond to the one or more conductive channels. The one or more bond pads on the bottom surface of the semiconductor substrate are coupled to bond pads on the another substrate using the controlled, collapse chip connection technique, which allows the top surface of the semiconductor substrate to be accessible for design verification or circuit test processes. The present invention further includes a controlled, collapse connection chip carrier system which includes a base substrate having one or more bond pads formed thereon and a circuit substrate having circuitry on a top surface thereof and one or more bonds pads on a bottom surface thereof which correspond generally to the one or more bond pads on the base substrate. The circuit substrate further includes one or more conductive channels extending therethrough which electrically couple selective portions of the circuitry on the top surface to the one or more bond pads on the bottom surface. The system further includes a controlled, collapse connection between the one or more bond pads on the base substrate and the one or more bond pads on the bottom surface of the circuit substrate which provides an electrical connection between the base substrate and selective portions of the circuitry on the top surface of the circuit substrate.

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