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1. 发明申请

US20050018482A1 TECHNIQUES FOR REDUCING EFFECTS OF COUPLING BETWEEN STORAGE ELEMENTS OF ADJACENT ROWS OF MEMORY CELLS 有权
标题翻译：减少存储单元存储容量存储元件之间耦合效应的技术
公开(公告)号：US20050018482A1
公开(公告)日：2005-01-27
申请号：US10923320
申请日：2004-08-20
申请人： Raul-Adrian Cemea , Khandker Quader , Yan Li , Jian Chen , Yupin Fong
发明人： Raul-Adrian Cemea , Khandker Quader , Yan Li , Jian Chen , Yupin Fong
IPC分类号： G11C16/02 , G11C11/56 , G11C16/10 , G11C16/34 , G11C11/34
CPC分类号： G11C16/3427 , G11C11/5628 , G11C16/10 , G11C16/3418
摘要： Techniques of reducing erroneous readings of the apparent charge levels stored in a number of rows of memory cells on account of capacitive coupling between the cells. All pages of a first row are programmed with a first pass, followed by programming all pages of a second adjacent row with a first pass, after which the first row is programmed with a second pass, and then all pages of a third row are programmed with a first pass, followed by returning to program the second row with a second pass, and so on, in a back-and-forth manner across the rows of an array. This minimizes the effect on the apparent charge stored on rows of memory cells that can occur by later writing data into adjacent rows of memory cells.
摘要翻译：考虑到电池之间的电容耦合，减少存储在多行存储器单元中的表观电荷水平的错误读数的技术。第一行的所有页面都用第一遍编程，然后用第一遍编程第二相邻行的所有页面，之后第一行以第二遍编程，然后第三行的所有页面都被编程第一遍，然后通过第二遍返回到第二行的程序，依次类推，跨越数组的行。这最大程度地减少了通过稍后将数据写入存储器单元的相邻行中可能发生的对存储器单元行存储的视在电荷的影响。

2. 发明申请

US20050146931A1 Techniques for reducing effects of coupling between storage elements of adjacent rows of memory cells 有权
公开(公告)号：US20050146931A1
公开(公告)日：2005-07-07
申请号：US11055776
申请日：2005-02-09
申请人： Raul-Adrian Cernea , Khandker Quader , Yan Li , Jian Chen , Yupin Fong
发明人： Raul-Adrian Cernea , Khandker Quader , Yan Li , Jian Chen , Yupin Fong
IPC分类号： G11C16/02 , G11C11/56 , G11C16/10 , G11C16/34 , G11C11/34 , G11C16/04
CPC分类号： G11C16/3427 , G11C11/5628 , G11C16/10 , G11C16/3418
摘要： Techniques of reducing erroneous readings of the apparent charge levels stored in a number of rows of memory cells on account of capacitive coupling between the cells. All pages of a first row are programmed with a first pass, followed by programming all pages of a second adjacent row with a first pass, after which the first row is programmed with a second pass, and then all pages of a third row are programmed with a first pass, followed by returning to program the second row with a second pass, and so on, in a back-and-forth manner across the rows of an array. This minimizes the effect on the apparent charge stored on rows of memory cells that can occur by later writing data into adjacent rows of memory cells.

3. 发明申请

US20050047223A1 Operating techniques for reducing effects of coupling between storage elements of a non-volatile memory operated in multiple data states 有权
公开(公告)号：US20050047223A1
公开(公告)日：2005-03-03
申请号：US10966451
申请日：2004-10-15
申请人： Jian Chen , Tomoharu Tanaka , Yupin Fong , Khandker Quader
发明人： Jian Chen , Tomoharu Tanaka , Yupin Fong , Khandker Quader
IPC分类号： G11C16/02 , G11C11/56 , G11C16/00 , G11C16/04 , G11C16/12 , G11C16/34 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/34
CPC分类号： G11C11/5628 , G11C11/5621 , G11C16/0483 , G11C16/12 , G11C16/3404 , G11C16/3418 , G11C16/3454 , G11C16/3459
摘要： A non-volatile memory system having an array of memory cells with at least one storage element each is operated with a plurality of storage level ranges per storage element. A flash electrically erasable and programmable read only memory (EEPROM) is an example, wherein the storage elements are electrically floating gates. The memory is operated to minimize the effect of charge coupled between adjacent floating gates, by programming some cells a second time after adjacent cells have been programmed. The second programming step also compacts a distribution of charge levels within at least some of the programming states. This increases the separation between states and/or allows more states to be included within a given storage window. An implementation that is described is for a NAND type of flash EEPROM.

4. 发明申请

US20050276101A1 Operating techniques for reducing effects of coupling between storage elements of a non-volatile memory operated in multiple data states 有权
标题翻译：用于减少在多个数据状态下操作的非易失性存储器的存储元件之间的耦合效应的操作技术
公开(公告)号：US20050276101A1
公开(公告)日：2005-12-15
申请号：US11205595
申请日：2005-08-16
申请人： Jian Chen , Tomoharu Tanaka , Yupin Fong , Khandker Quader
发明人： Jian Chen , Tomoharu Tanaka , Yupin Fong , Khandker Quader
IPC分类号： G11C16/02 , G11C11/56 , G11C16/00 , G11C16/04 , G11C16/12 , G11C16/34 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C11/5628 , G11C11/5621 , G11C16/0483 , G11C16/12 , G11C16/3404 , G11C16/3418 , G11C16/3454 , G11C16/3459
摘要： A non-volatile memory system having an array of memory cells with at least one storage element each is operated with a plurality of storage level ranges per storage element. A flash electrically erasable and programmable read only memory (EEPROM) is an example, wherein the storage elements are electrically floating gates. The memory is operated to minimize the effect of charge coupled between adjacent floating gates, by programming some cells a second time after adjacent cells have been programmed. The second programming step also compacts a distribution of charge levels within at least some of the programming states. This increases the separation between states and/or allows more states to be included within a given storage window. An implementation that is described is for a NAND type of flash EEPROM.
摘要翻译：具有每个具有至少一个存储元件的存储器单元阵列的非易失性存储器系统每个存储元件具有多个存储级别范围。闪存电可擦除和可编程只读存储器（EEPROM）是示例，其中存储元件是电浮动栅极。操作存储器以通过在相邻单元被编程之后第二次编程一些单元来最小化耦合在相邻浮动栅极之间的电荷的影响。第二编程步骤还压缩至少一些编程状态下的电荷水平分布。这增加了状态之间的分离和/或允许在给定的存储窗口内包含更多的状态。所描述的实现方案是用于NAND型闪存EEPROM。

5. 发明申请

US20070058435A1 Read and erase verify methods and circuits suitable for low voltage non-volatile memories 有权
标题翻译：读取和擦除适用于低电压非易失性存储器的验证方法和电路
公开(公告)号：US20070058435A1
公开(公告)日：2007-03-15
申请号：US10552948
申请日：2004-04-08
申请人： Jian Chen , Khandker Quader
发明人： Jian Chen , Khandker Quader
IPC分类号： G11C11/34
CPC分类号： G11C7/04 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0483 , G11C16/16 , G11C16/20 , G11C16/26 , G11C16/344 , G11C16/3445 , G11C16/3459 , G11C2211/5621
摘要： In a non-volatile memory, the read parameter used to distinguish the data states characterized by a negative threshold voltage from the data states characterized by a positive threshold voltage is compensated for the memory's operating conditions, rather than being hardwired to ground. In an exemplary embodiment, the read parameter for the data state with the lowest threshold value above ground is temperature compensated to reflect the shifts of the storage element populations on either side of the read parameter. According to another aspect, an erase process is presented that can take advantage the operating condition compensated sensing parameter. As the sensing parameter is no longer fixed at a value corresponding to 0 volts, instead shifting according to operating conditions, a sufficient margin is provided for the various erase verify levels even at lowered operating voltages.
摘要翻译：在非易失性存储器中，用于区分由负阈值电压表征的数据状态的读取参数与由正阈值电压表征的数据状态进行补偿，而不是硬连线到地。在示例性实施例中，对于具有高于地面的最低阈值的数据状态的读取参数被温度补偿以反映存储元件群在读取参数的任一侧上的偏移。根据另一方面，提出了可以利用操作条件补偿的感测参数的擦除过程。由于感测参数不再固定为对应于0伏的值，而是根据工作条件进行移位，即使在降低的工作电压下，也为各种擦除验证电平提供足够的余量。

6. 发明申请

US20060028876A1 Erase inhibit in non-volatile memories 有权
标题翻译：擦除非易失性存储器中的禁止
公开(公告)号：US20060028876A1
公开(公告)日：2006-02-09
申请号：US11223055
申请日：2005-09-08
申请人： Khandker Quader , Raul-Adrian Cernea
发明人： Khandker Quader , Raul-Adrian Cernea
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/3427 , G11C16/0483 , G11C16/14 , G11C16/16 , G11C16/3418
摘要： The present invention presents a non-volatile memory and method for its operation that can reduce the amount of disturb in non-selected cells during an erase process. For a set of storage elements formed over a common well structure, all word-lines are initially charged with the same high voltage erase signal that charges the well to insure there is no net voltage difference between the well and word-lines. The selected word-lines are then discharged to ground while the non-selected word-lines and the well are maintained at the high voltage. According to another aspect of the present invention, this can be accomplished without increasing any pitch area circuit or adding new wires in the memory array, and at minimal additional peripheral area. Advantages include less potential erase disturb in the non-selected storage elements and a tighter erase distribution for the selected elements.
摘要翻译：本发明提供一种用于其操作的非易失性存储器和方法，其可以在擦除处理期间减少未选择的单元的干扰量。对于在公共阱结构上形成的一组存储元件，所有字线最初都以相同的高电压擦除信号充电，以确保阱和字线之间没有净电压差。所选择的字线然后放电到地，而未选择的字线和阱保持在高电压。根据本发明的另一方面，这可以在不增加任何音调区域电路或在存储器阵列中添加新的线以及在最小额外周边区域的情况下实现。优点包括在未选择的存储元件中较少的电位擦除干扰以及所选元件的更严格的擦除分布。

7. 发明申请

US20060023507A1 Method of reducing disturbs in non-volatile memory 有权
公开(公告)号：US20060023507A1
公开(公告)日：2006-02-02
申请号：US11238911
申请日：2005-09-28
申请人： John Mangan , Daniel Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang , Khandker Quader
发明人： John Mangan , Daniel Guterman , George Samachisa , Brian Murphy , Chi-Ming Wang , Khandker Quader
IPC分类号： G11C7/10 , G11C11/34
CPC分类号： G11C7/12 , G11C16/12 , G11C16/3427 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50012 , G11C2029/1204
摘要： In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these. In a second, complementary aspect, the rate at which the voltage levels on the bit lines are changed is adjustable. By monitoring the frequency of disturbs, or based upon the device's application, the rate at which the bit line drivers change the bit line voltage can be adjusted. This can be implemented by setting the rate externally, or by the controller based upon device performance and the amount of data error being generated.

8. 发明申请

US20050068808A1 ERASE INHIBIT IN NON-VOLATILE MEMORIES 有权
标题翻译：消除非易失性存储器中的消除
公开(公告)号：US20050068808A1
公开(公告)日：2005-03-31
申请号：US10671847
申请日：2003-09-25
申请人： Khandker Quader , Raul-Adrian Cernea
发明人： Khandker Quader , Raul-Adrian Cernea
IPC分类号： G11C11/34 , G11C16/04 , G11C16/14 , G11C16/16 , G11C16/34
CPC分类号： G11C16/3427 , G11C16/0483 , G11C16/14 , G11C16/16 , G11C16/3418
摘要： The present invention presents a non-volatile memory and method for its operation that can reduce the amount of disturb in non-selected cells during an erase process. For a set of storage elements formed over a common well structure, all word-lines are initially charged with the same high voltage erase signal that charges the well to insure there is no net voltage difference between the well and word-lines. The selected word-lines are then discharged to ground while the non-selected word-lines and the well are maintained at the high voltage. According to another aspect of the present invention, this can be accomplished without increasing any pitch area circuit or adding new wires in the memory array, and at minimal additional peripheral area. Advantages include less potential erase disturb in the non-selected storage elements and a tighter erase distribution for the selected elements.
摘要翻译：本发明提供一种用于其操作的非易失性存储器和方法，其可以在擦除处理期间减少未选择的单元的干扰量。对于在公共阱结构上形成的一组存储元件，所有字线最初都以相同的高电压擦除信号充电，以确保阱和字线之间没有净电压差。所选择的字线然后放电到地，而未选择的字线和阱保持在高电压。根据本发明的另一方面，这可以在不增加任何音调区域电路或在存储器阵列中添加新的线以及在最小额外周边区域的情况下实现。优点包括在未选择的存储元件中较少的电位擦除干扰以及所选元件的更严格的擦除分布。

9. 发明申请

US20060077712A1 Non-volatile semiconductor memory device, electronic card using the same and electronic apparatus 有权
标题翻译：非易失性半导体存储器件，使用其的电子卡和电子设备
公开(公告)号：US20060077712A1
公开(公告)日：2006-04-13
申请号：US11289509
申请日：2005-11-30
申请人： Tomoharu Tanaka , Khandker Quader , Hiroyuki Dohmae , Atsushi Inoue , Takeaki Sato
发明人： Tomoharu Tanaka , Khandker Quader , Hiroyuki Dohmae , Atsushi Inoue , Takeaki Sato
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G06K19/07732 , G11C7/1045 , G11C16/26 , G11C16/32
摘要： Disclosed is a non-volatile semiconductor memory device comprising a plurality of non-volatile semiconductor memory cells, an interface making data exchange with an external device to write/read data with respect to the non-volatile semiconductor memory cells, and a control circuit for controlling the non-volatile semiconductor memory cells, wherein the interface and the control circuit include a first read mode initialized via a first bootstrap to read data from the non-volatile semiconductor memory cells for continuously outputting (N+M)-byte (N is the n-th power of 2, n is positive integers) data via the interface, and a second read mode initialized via a second bootstrap to read data from the non-volatile semiconductor memory cells for continuously outputting K-byte (K is the k-th power of 2, k is positive integers) data via the interface.
摘要翻译：公开了一种包括多个非易失性半导体存储单元的非易失性半导体存储器件，与外部器件进行数据交换以对非易失性半导体存储单元进行写/读数据的接口，以及用于控制所述非易失性半导体存储单元，其中所述接口和所述控制电路包括经由第一自举初始化的第一读取模式，以从所述非易失性半导体存储单元读取数据，以连续输出（N + M）字节（N为经由接口的n的n次幂，n是正整数）数据，以及经由第二引导来初始化的第二读取模式，以从非易失性半导体存储器单元读取用于连续输出K字节的数据（K是k 功率为2，k为正整数）数据。

10. 发明申请

US20060007736A1 Method and system for programming and inhibiting multi-level, non-volatile memory cells 有权
公开(公告)号：US20060007736A1
公开(公告)日：2006-01-12
申请号：US11223709
申请日：2005-09-09
申请人： Khandker Quader , Khanh Nguyen , Feng Pan , Long Pham , Alexander Mak
发明人： Khandker Quader , Khanh Nguyen , Feng Pan , Long Pham , Alexander Mak
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/3486
摘要： A multi-level non-volatile memory cell programming/lockout method and system are provided. The programming/lockout method and system advantageously prevent memory cells that charge faster than other memory cells from being over-programmed.

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