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1. 发明授权

US06847378B2 System and method for performing scale and bias operations by preclamping input image data 有权
标题翻译：通过预压缩输入图像数据进行缩放和偏移操作的系统和方法
公开(公告)号：US06847378B2
公开(公告)日：2005-01-25
申请号：US10093364
申请日：2002-03-07
申请人： Ranjit S. Oberoi , Michael G. Lavelle , Anthony S. Ramirez
发明人： Ranjit S. Oberoi , Michael G. Lavelle , Anthony S. Ramirez
IPC分类号： G06T3/40 , G09G5/36 , G09G5/02
CPC分类号： G06T3/4007 , G09G5/363
摘要： In one embodiment, a scale and bias unit for use in a graphics system includes a preclamping unit configured to receive an input and to responsively generate an output value equal to a first value if the input is within a first input range. The scale and bias unit also includes a processing unit coupled to the preclamping unit and configured to perform a calculation on the input to generate the output value. The processing unit does not perform the calculation if the input is within the first input range.
摘要翻译：在一个实施例中，用于图形系统的比例尺和偏置单元包括预压缩单元，其被配置为接收输入并且如果输入在第一输入范围内则响应地产生等于第一值的输出值。缩放和偏置单元还包括耦合到预压单元并被配置为对输入执行计算以产生输出值的处理单元。如果输入在第一输入范围内，则处理单元不执行计算。

2. 发明授权

US06847369B2 Optimized packing of loose data in a graphics queue 有权
标题翻译：在图形队列中优化了松散数据的打包
公开(公告)号：US06847369B2
公开(公告)日：2005-01-25
申请号：US10060915
申请日：2002-01-30
申请人： Michael G. Lavelle , Ewa M. Kubalska , Anthony S. Ramirez , Huang Pan
发明人： Michael G. Lavelle , Ewa M. Kubalska , Anthony S. Ramirez , Huang Pan
IPC分类号： G06T1/60 , G09G5/36
CPC分类号： G09G5/363 , G06T1/60
摘要： A data queue optimized for receiving loosely packed graphics data and suitable for use in a computer graphics system is described. The data queue operates on first-in-first-out principals, and has a variable width input and output. The variable width on the input side facilitates the reception and storage of loosely packed data. The variable width output allows for the single-cycle output of multi-word data. Packing of the data occurs on the write-side of the FIFO structure.
摘要翻译：描述了优化用于接收松散封装的图形数据并适合于在计算机图形系统中使用的数据队列。数据队列以先进先出原则进行操作，并具有可变宽度的输入和输出。输入侧的可变宽度有助于松散打包数据的接收和存储。可变宽度输出允许多字数据的单周期输出。数据的包装发生在FIFO结构的写入端。

3. 发明授权

US06816161B2 Vertex assembly buffer and primitive launch buffer 有权
标题翻译：顶点汇编缓冲区和原始启动缓冲区
公开(公告)号：US06816161B2
公开(公告)日：2004-11-09
申请号：US10060969
申请日：2002-01-30
申请人： Michael G. Lavelle , Huang Pan , Anthony S. Ramirez
发明人： Michael G. Lavelle , Huang Pan , Anthony S. Ramirez
IPC分类号： G06F1300
CPC分类号： G06T15/005
摘要： A graphics system and method for processing geometry compressed, three-dimensional graphics data are disclosed. After transforming and lighting each vertex, a vertex data stream is decompressed using connectivity information, and vertexes are reassembled into geometric primitives. The connectivity information may include mesh buffer references, vertex tags, or other types of information. Independent buffers, queues, and/or caches are used to simultaneously store: (a) vertex data for the next several primitives, (b) vertex data that will be reused, (c) vertex tags, (d) control tags, (e) vertex data being assembled into a primitive, and (f) an assembled primitive ready to be launched. The assembled primitive may be clip tested for visibility in a defined viewport, before investing time to have the primitive processed into pixel data for display. The independent buffers, queues, and/or caches may also enable the vertex processing steps to be performed in parallel and at different rates.
摘要翻译：公开了用于处理几何压缩的三维图形数据的图形系统和方法。在对每个顶点进行变换和点亮之后，使用连通性信息解压缩顶点数据流，并将顶点重新组合成几何图元。连接信息可以包括网格缓冲器引用，顶点标签或其他类型的信息。独立缓冲区，队列和/或高速缓存用于同时存储：（a）下一个原语的顶点数据，（b）将被重用的顶点数据，（c）顶点标签，（d）控制标签，（e ）顶点数据被组装成原始图形，（f）准备启动的组合原始图形。在投入时间以将原始图像处理成像素数据进行显示之前，组合的原始图像可以在定义的视口中进行剪辑测试。独立缓冲器，队列和/或高速缓存也可以使顶点处理步骤以并行且不同的速率执行。

4. 发明授权

US06957399B2 Controlling the propagation of a digital signal by means of variable I/O delay compensation using delay-tracking 有权
标题翻译：通过使用延迟跟踪的可变I / O延迟补偿来控制数字信号的传播
公开(公告)号：US06957399B2
公开(公告)日：2005-10-18
申请号：US10317740
申请日：2002-12-12
申请人： Brian D. Emberling , Anthony S. Ramirez
发明人： Brian D. Emberling , Anthony S. Ramirez
IPC分类号： G06F13/16 , G06F17/50
CPC分类号： G06F13/1689
摘要： The propagation of a feedback signal, such as a DQS signal generated in response to a read request in a Double Data Rate (DDR) memory system, into a digital host system, such as an ASIC, is controlled by using delay tracking to compensate for variable I/O delay. The memory system includes a controller and an interface, both on the ASIC, and memory units coupled to the controller through the interface, all configured on a printed circuit board (PCB). The interface uses the read request signal, sent by the controller to initiate read operations, to generate a read-enable signal, which is transmitted to a trace on the PCB one-half cycle of the system clock before DQS is expected to reach the interface. The trace tracks the total delay encountered by the system clock and DQS between the interface unit and memory units, and is routed back to the interface unit, where read-enable is used to generate an enable signal that allows DQS to propagate into the ASIC only when DQS is a valid digital signal.
摘要翻译：将响应于双数据速率（DDR）存储器系统中的读取请求而产生的DQS信号的反馈信号（例如ASIC）传播到诸如ASIC的数字主机系统中，通过使用延迟跟踪来补偿可变I / O延迟。该存储器系统包括控制器和接口，ASIC和存储器单元通过接口耦合到控制器，全部配置在印刷电路板（PCB）上。该接口使用由控制器发送的读取请求信号来启动读取操作，以产生读取使能信号，该信号在DQS预期到达接口之前被传送到系统时钟的PCB半个周期的轨迹上。跟踪跟踪系统时钟和接口单元与存储单元之间的DQS所遇到的总延迟，并将其路由回接口单元，在该单元中使用读使能来产生允许DQS传播到ASIC的使能信号当DQS是有效的数字信号时。

5. 发明授权

US06885375B2 Stalling pipelines in large designs 有权
标题翻译：大型设计中的管道不畅
公开(公告)号：US06885375B2
公开(公告)日：2005-04-26
申请号：US10095308
申请日：2002-03-11
申请人： Brian D. Emberling , Ewa M. Kubalska , Steve Kurihara , Anthony S. Ramirez , Andre J. Gaytan
发明人： Brian D. Emberling , Ewa M. Kubalska , Steve Kurihara , Anthony S. Ramirez , Andre J. Gaytan
IPC分类号： G06T1/20
CPC分类号： G06T1/20
摘要： A method and a system for stalling large pipelined designs. A computational pipeline may comprise a first module and a second module coupled together. The first module may propagate one or more signals to the second module. A stall-signal may be asserted in order to stall the computational pipeline if the second module is not ready to receive the one or more signals from the first module. The one or more signals propagated from the first module and the asserted stall-signal may be buffered in a stall-buffer. The asserted stall-signal may be propagated to the first module in a next cycle. The first module may be stalled in response to the first module receiving the propagated asserted stall-signal. Next, the asserted stall-signal may be propagated up the computational pipeline.
摘要翻译：一种阻止大流水线设计的方法和系统。计算流水线可以包括耦合在一起的第一模块和第二模块。第一模块可以将一个或多个信号传播到第二模块。如果第二模块未准备好接收来自第一模块的一个或多个信号，则可以断言失速信号以便停止计算流水线。从第一模块传播的一个或多个信号和被断言的失速信号可以缓冲在停顿缓冲器中。在下一个周期中，断言的失速信号可以传播到第一个模块。第一模块可以响应于第一模块接收传播的断言失速信号而停止。接下来，所断言的失速信号可以在计算流水线上传播。

6. 发明授权

US07089509B2 Controlling the propagation of a control signal by means of variable I/O delay compensation using a programmable delay circuit and detection sequence 有权
标题翻译：通过使用可编程延迟电路和检测顺序的可变I / O延迟补偿来控制控制信号的传播
公开(公告)号：US07089509B2
公开(公告)日：2006-08-08
申请号：US10328565
申请日：2002-12-23
申请人： Brian D. Emberling , Anthony S. Ramirez
发明人： Brian D. Emberling , Anthony S. Ramirez
IPC分类号： G06F17/50 , G06F12/00
CPC分类号： G06F13/1689
摘要： The propagation of a feedback signal, such as a DQS signal generated in response to a read request in a Double Data Rate (DDR) memory system, into a digital host system, such as an ASIC, is controlled by using a programmable delay circuit and detection sequence to compensate for variable I/O delay. The memory system includes a controller and an interface, both on the ASIC, and memory units coupled to the controller through the interface. The interface uses the read request signal, sent by the controller to initiate read operations, to generate a select signal. A programmable delay element inside the interface unit is programmed using a delay value generated by a delay manager unit inside the controller. The programmable delay element delays the select signal, and an enable signal is generated from the delayed select signal, using DQS. The propagation of DQS is controlled by the enable signal. For a number of preferred delay values that are determined through the detection sequence, the enable signal allows DQS to propagate into the ASIC only when DQS is a valid digital signal.
摘要翻译：通过使用可编程延迟电路来控制反馈信号（例如响应于双数据速率（DDR）存储器系统中的读取请求而生成的DQS信号）到数字主机系统（例如ASIC）中的传播，检测顺序来补偿可变I / O延迟。存储器系统包括ASIC上的控制器和接口，以及通过接口耦合到控制器的存储器单元。该接口使用由控制器发送的读取请求信号来启动读取操作，以产生选择信号。使用由控制器内的延迟管理器单元生成的延迟值来编程接口单元内的可编程延迟元件。可编程延迟元件延迟选择信号，使用DQS从延迟选择信号产生使能信号。 DQS的传播由使能信号控制。对于通过检测序列确定的多个优选延迟值，使能信号仅在DQS为有效数字信号时才允许DQS传播到ASIC。

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